Vertical Field Effect Transistors for 3D NAND Memory Integration
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Solution Overview
Problem
Current semiconductor technologies face challenges in creating compact three-dimensional memory devices with efficient vertical field effect transistors that can effectively integrate with three-dimensional NAND memory arrays, requiring innovative methods for transistor formation and bonding to enhance performance and density.
Innovation Solution
The formation of bonded assemblies comprising a memory die with a three-dimensional memory array and a logic die with vertical field effect transistors, where each transistor includes a bottom doped semiconductor electrode, a vertical transistor channel surrounded by a gate dielectric, and a top doped semiconductor electrode, with electrical connections through metal bonding pads, enabling efficient integration and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional lateral field effect transistors are used in three-dimensional memory devices, then the device structure is simpler to manufacture, but the memory device occupies larger area and has reduced density
Solution Approach 1:
The patent transitions from conventional lateral field effect transistors to vertical field effect transistors, changing the transistor architecture from two-dimensional planar structure to three-dimensional vertical structure. This dimensional change allows the transistors to be stacked vertically above the memory array, significantly reducing the footprint area and increasing memory density while maintaining manufacturability through adapted fabrication processes
2Quantity of substance
If vertical field effect transistors are implemented, then memory device density is enhanced, but the transistor structure and bonding process become more complex
Solution Approach 1:
The patent divides the memory device into separate functional components: a memory array die and a logic die with vertical transistors. This segmentation allows each component to be optimized and fabricated independently, then bonded together. The vertical transistors are segmented into distinct layers including bottom electrodes, gate structures, channels, and top electrodes, enabling modular fabrication and assembly while achieving high density
3Reliability
If vertical field effect transistors with surrounding gate structures are used, then transistor control efficiency is improved, but the manufacturing process requires additional steps
Solution Approach 1:
The patent implements a surrounding gate structure where the gate electrode is positioned to encircle the channel region vertically. This nested configuration, with the gate wrapping around the channel like a doll inside another doll, provides enhanced electrostatic control over the charge carriers in the channel, improving transistor switching efficiency and reliability while managing the increased manufacturing complexity through structured process integration
4Adaptability or versatility
If bonded assembly of memory die and logic die is implemented, then functional integration is enhanced, but the bonding process and electrical connection become more complex
Solution Approach 1:
The patent merges the memory array functionality on one die with the logic circuit functionality containing vertical transistors on another die through direct bonding. The bonding process integrates the two separately optimized dies into a single functional assembly, enabling enhanced versatility by combining different functional elements while managing the bonding complexity through precise alignment and connection of corresponding electrical contacts between the dies
Data Source
AI summary
A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom doped semiconductor electrode, a vertical transistor channel, a cylindrical gate dielectric, and a top doped semiconductor electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.