Vertical FET Abrupt Junction via Low-Temp Epitaxy
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Solution Overview
Problem
Conventional vertical transistors face challenges in creating a bottom source/drain structure with an abrupt junction profile due to the high thermal budget required, which results in a broad dopant profile, making it difficult to achieve an abrupt junction at the interface of the bottom source/drain extension region and sidewall surfaces of a semiconductor fin.
Innovation Solution
A semiconductor structure is developed with a vertical transport field effect transistor featuring an abrupt junction between the bottom source/drain extension region and the sidewall surfaces of a semiconductor fin, achieved through a method that includes forming a semiconductor fin with a hard mask cap, recessing the substrate to create a mesa portion, and forming a bottom source/drain structure that contacts the sidewall surfaces of the fin without the need for a high thermal budget, allowing for an epitaxial growth of the source/drain extension region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a high thermal budget (800°C or greater) is used to drive-in dopants from the bottom source/drain structure, then dopants are successfully driven into the semiconductor material to form bottom extension regions, but the dopant profile becomes broad instead of abrupt
Solution Approach 1:
The patent changes the temperature parameter from high (800°C or greater) to low (below 800°C) to achieve abrupt junction profiles. By reducing the thermal budget, the dopant diffusion is controlled to maintain sharp concentration gradients at the junction interface, transforming the broad dopant profile into an abrupt one through epitaxial growth rather than thermal drive-in.
2Manufacturing precision
If conventional high thermal budget processes are used, then bottom source/drain extension regions are formed, but the junction profile at the interface with semiconductor fin sidewalls becomes broad rather than abrupt
Solution Approach 1:
The patent applies preliminary action by forming the bottom source/drain structure with dopants already incorporated at low temperature, then using epitaxial growth to extend the semiconductor material with abrupt junctions. This preliminary doping followed by low-temperature epitaxial growth replaces the conventional high-temperature drive-in process, achieving abrupt profiles without complex thermal management.
3Reliability
If high thermal budget is applied to drive-in dopants, then bottom extension regions are formed, but the resulting dopant profile is broad which degrades device performance
Solution Approach 1:
The patent inverts the conventional approach by performing doping and extension region formation at low temperatures through epitaxial growth, rather than using high-temperature drive-in processes. This inversion of the traditional thermal budget approach enables abrupt junction profiles that enhance device performance while avoiding the performance-degrading effects of high-temperature processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of a semiconductor structure with an abrupt junction, improving the sharpness of the dopant profile and reducing thermal budget requirements, thus enhancing the performance and scalability of vertical transistors for technology beyond 5 nm.
Implementation Method 1
achieved through a method that includes forming a semiconductor fin with a hard mask cap, recessing the substrate to create a mesa portion, and forming a bottom source/drain structure that contacts the sidewall surfaces of the fin without the need for a high thermal budget, allowing for an epitaxial growth of the source/drain extension region
Data Source
AI summary
A semiconductor structure is provided that includes a vertical transport field effect transistor located on sidewall surfaces of a semiconductor fin. The semiconductor structure further includes an abrupt junction that is located between a bottom source/drain extension region and a sidewall surface of a lower portion of the semiconductor fin. The bottom source/drain extension region is present in a gap that is located adjacent the lower portion of the semiconductor fin and atop a mesa portion of a base semiconductor substrate.