Vertical FET with Air-Gaps and Epitaxial Source-Drain
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Solution Overview
Problem
Multi-gate FETs face challenges with high parasitic resistance due to ultra-thin body channels, which affect performance and scalability in CMOS technology.
Innovation Solution
The method involves forming fins over a semiconductor substrate, creating a bottom source/drain region, and using high-k metal gates with epitaxial material and air-gaps to reduce contact resistance and parasitic capacitance, incorporating a silicide metal liner and conductive material to enhance silicidation area and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multi-gate FETs are used to control channel current, then switching speed is improved, but parasitic resistance increases due to ultra-thin body channels
Solution Approach 1:
The patent transitions from planar FET architecture to vertical multi-gate FET architecture, changing the dimensional orientation of the channel from horizontal to vertical. This allows the gate to wrap around the channel from multiple sides (top, bottom, and sidewalls), providing enhanced control over the ultra-thin body channel while maintaining compact footprint. The vertical configuration enables effective electrostatic control of the channel despite the reduced channel thickness that causes parasitic resistance issues.
Solution Approach 2:
The patent implements a nested structure where the gate electrode is positioned within recesses formed in the insulating layer, surrounding the vertical channel from multiple directions. The gate wraps around the channel in a nested configuration, with the channel embedded within the gate structure. This multi-directional gating provides superior control over the channel current while minimizing parasitic resistance effects through enhanced electrostatic management.
2Speed
If channel length is reduced to increase switching speed, then speed is improved, but control over short channel effects and punch-through deteriorates
Solution Approach 1:
The patent employs vertical channel orientation with gate electrodes positioned at multiple levels (top gate and bottom gate) to provide three-dimensional control over the channel. This multi-dimensional gating configuration enables effective control of short channel effects even when the channel length is reduced, as the gate electric field extends throughout the vertical channel from multiple directions, preventing punch-through and maintaining electrostatic control.
Solution Approach 2:
The nested gate structure with top and bottom gates surrounding the vertical channel provides enhanced electrostatic control. The gate electrodes are positioned in recesses that allow them to wrap around the channel, creating a nested configuration where the channel is surrounded by gating structures from multiple directions. This provides superior control over short channel effects and punch-through phenomena.
3Loss of energy
If MOS leakage current is reduced by thinning the channel, then leakage is reduced, but parasitic resistance increases
Solution Approach 1:
The patent uses a nested multi-gate configuration where top and bottom gates surround the ultra-thin vertical channel from multiple directions. This provides enhanced electrostatic control over the depleted channel region, effectively suppressing MOS leakage current through improved field effect. Simultaneously, the close proximity of the gates to the channel and the vertical configuration reduce the parasitic resistance by minimizing the distance for carrier transport and improving contact geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contact resistance and parasitic capacitance, improving the performance and scalability of multi-gate FETs by increasing the silicidation area and creating air-gaps, leading to better control over channel resistance and capacitance.
Implementation Method 1
depositing an epitaxial material over the top sections of the plurality of fins
Implementation Method 2
forming a dielectric film over the epitaxial material such that air-gaps are created between the top sections of the plurality of fins
Data Source
AI summary
A method is presented for reducing contact resistance and parasitic capacitance. The method includes forming a plurality of fins over a semiconductor substrate, forming a bottom source/drain region between the plurality of fins, forming a bottom spacer over the bottom source/drain region, forming high-k metal gates over the bottom spacers, and forming a top spacer over the high-k metal gates. The method further includes forming an interlayer dielectric (ILD) over the top spacer, recessing the ILD to expose top sections of the plurality of fins, depositing an epitaxial material over each of the top sections of the plurality of fins, forming a dielectric film over the epitaxial material such that air-gaps are created between the top sections of the plurality of fins and recessing the dielectric film to expose top sections of the epitaxial material and to deposit a silicide metal liner and a conductive material thereon.