Vertical FET Backside Gate Contact for Contact Space and Resistance
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Solution Overview
Problem
Fin field-effect transistor (FiN-FET) devices face challenges with reduced space for metal gate and source/drain contacts as they are scaled down, leading to degraded short-channel control and increased middle-of-the-line resistance.
Innovation Solution
The implementation of a backside gate contact extending from a frontside gate structure into a backside interlevel dielectric layer, connected by a backside metal via, alleviates the overcrowding issue on the frontside of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If horizontal FiN-FET devices are scaled down, then device size is reduced, but space for metal gate and source/drain contacts is reduced leading to degraded short-channel control and increased middle-of-the-line resistance
Solution Approach 1:
The patent transitions from horizontal current flow to vertical current flow in the channel, moving the device architecture from a planar configuration to a three-dimensional vertical structure. This dimensional change allows contacts to be positioned at the top and bottom of the vertical channel rather than at lateral ends, providing additional spatial freedom for contact placement and improving short-channel control through better gate coverage.
2Length of moving object
If horizontal FiN-FET devices are scaled down, then device size is reduced, but middle-of-the-line resistance increases due to reduced space for contacts
Solution Approach 1:
By transitioning to vertical FET architecture, the patent enables contact placement at the top and bottom surfaces of the vertical channel structure. This three-dimensional arrangement provides additional space for optimized contact dimensions and positioning, allowing for larger contact areas and better electrical connections that reduce middle-of-the-line resistance even as device footprint is reduced.
3Adaptability or versatility
If vertical FET structure is implemented, then scalability is improved and short-channel control is enhanced, but device complexity increases with additional liner layers and backside contacts
Solution Approach 1:
The patent divides the gate structure into frontside and backside components, with separate liner layers (first liner layer on frontside, second liner layer on backside) and distinct contact structures (frontside source/drain contacts and backside gate contact). This segmentation allows independent optimization of each component and simplifies the fabrication process by enabling separate processing steps for frontside and backside features.
Solution Approach 2:
The patent introduces liner layers as intermediary structures between the gate structure and surrounding materials, and between contacts and underlying layers. These liner layers serve as buffer and interface layers that facilitate controlled electrical connections and provide structural support, managing the complexity of the vertical architecture through well-defined intermediate components.
Data Source
AI summary
A semiconductor structure includes a gate structure disposed between a first vertical field-effect transistor and a second vertical field-effect transistor, a first liner layer disposed on the gate structure and a sidewall of the first vertical field-effect transistor and the second vertical field-effect transistor, a second liner layer disposed on the gate structure and a sidewall of the second vertical field-effect transistor, a backside gate contact between opposing sidewalls of the first liner layer and the second liner layer and having a first surface disposed on the gate structure, and a backside metal via disposed on a second surface of the backside gate contact. The first surface of the backside gate contact has a first width and the second surface of the backside gate contact has a second width greater than the first width.