Vertical FET Bilayer Bottom Spacer Alignment

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Solution Overview

Problem

Existing methods for forming bottom spacers in vertical field-effect transistors (VFETs) face challenges such as non-uniform spacer height variations, contamination diffusion, and flare-up issues, leading to increased resistance and degradation of the bottom junction, due to sensitive directional deposition processes like HDP CVD.

Innovation Solution

A method involving the formation of a bilayer bottom spacer with a first and second spacer layer, where each layer is made of the same or different dielectric materials, providing symmetrical straight alignment at the bottom junction, perpendicular to the fin and parallel to the substrate, to prevent flare-up and ensure uniform thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If directional deposition process (HDP CVD) is used to form bottom spacers, then spacer formation is achieved, but non-uniform spacer height variations and flare-up issues occur leading to increased resistance

Engineering Contradiction:
Improvespacer height uniformityVSAvoidbottom junction resistance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The bottom spacer is segmented into two distinct layers: a first spacer layer deposited conformally around the fin, and a second spacer layer deposited directionally on top. This segmentation allows the first layer to provide uniform baseline thickness while the second layer adds height control, resolving the contradiction between uniformity and resistance issues.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the spacer structure are assigned different qualities through the bilayer approach. The first spacer layer provides conformal coverage with uniform thickness for structural integrity, while the second spacer layer provides directional height control. This local differentiation eliminates flare-up and achieves both uniformity and low resistance.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If directional deposition process is used, then spacer formation is achieved, but contamination diffusion occurs degrading the bottom junction

Engineering Contradiction:
Improvespacer formation processVSAvoidcontamination diffusion
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The first spacer layer acts as an intermediary barrier between the fin structure and the directional deposition process. It provides a conformal base layer that protects the fin from direct exposure to contaminants during the second directional deposition, enabling easier manufacturing while preventing contamination diffusion.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If single layer spacer is used, then process simplicity is maintained, but alignment precision and flare-up control are insufficient

Engineering Contradiction:
Improvespacer structureVSAvoidbottom junction alignment
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The spacer structure is divided into two functional layers with distinct deposition methods. The first layer ensures conformal coverage for baseline precision, while the second layer provides directional height control. This segmentation achieves high alignment precision without excessive overall complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bilayer spacer structure combines two different deposition approaches (conformal and directional) into a composite structure. This composite approach leverages the advantages of both methods to achieve superior alignment precision and flare-up control while managing complexity.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in improved alignment and reduced resistance between the source/drain and gate structures, enhancing the performance and stability of the VFETs by maintaining uniform spacer thickness and preventing contamination diffusion.

Implementation Method 1

The directional deposition process often requires additional treatments aimed at removing deposited materials from fin sidewalls of the VFET

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

directional deposition process like HDP CVD

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS10943992B2Transistor having straight bottom spacers
Publication Date: 2021.03.09 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10943992B2 patent drawing
  • US10943992B2 patent drawing
  • US10943992B2 patent drawing

AI summary

An integrated semiconductor device having a substrate and a vertical field-effect transistor (FET) disposed on the substrate. The vertical FET includes a fin and a bottom spacer. The bottom spacer further includes a first spacer layer and a second spacer layer formed on top of the first spacer layer. The bottom spacer provides for a symmetrical straight alignment at a bottom junction between the bottom spacer and the fin.