Vertical FET Bottom Junction Epitaxy

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Solution Overview

Problem

Conventional methods for forming bottom junctions in vertical FET devices face challenges in achieving precise control over dopant placement and uniformity, leading to variability in device performance and access resistance.

Innovation Solution

The method involves creating recesses in a semiconductor substrate using sacrificial layers and spacers, followed by epitaxial growth of semiconductor material and in-situ doped selective epitaxy to form a quasi uniform bottom plate that merges with the channel, allowing for self-aligned doping and reduced access resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional methods are used to form bottom junctions, then the process is simpler, but dopant placement precision and uniformity deteriorate

Engineering Contradiction:
Improvedopant placement precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming sacrificial layers and spacers before the actual doping process. The sacrificial layers are deposited and patterned first, followed by spacer formation, which defines the precise locations where dopants will later be introduced. This preparatory structure ensures accurate dopant placement without requiring complex real-time control during doping.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses sacrificial layers and spacers as intermediary structures to achieve precise dopant placement. These intermediary elements serve as templates that guide dopant introduction, allowing indirect control over dopant positions. The spacers act as mediators that define the exact regions where dopants should be placed, improving precision without direct manipulation during doping.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If conventional doping methods are used, then the process is faster, but junction uniformity along fin length deteriorates

Engineering Contradiction:
Improvejunction uniformityVSAvoidprocessing speed
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent applies local quality by creating distinct regions with different properties through the spacer structure. The spacers define specific local zones along the fin where dopants are introduced, ensuring uniform dopant distribution in each localized region. This local control mechanism ensures consistent junction characteristics along the entire fin length, as each segment receives precisely controlled dopant amounts.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the doping process into discrete regions defined by the spacer structures. Instead of uniform doping across the entire fin, the process is divided into separate segments corresponding to different spacer locations. This segmentation allows independent control of dopant placement in each region, ensuring uniformity across the whole structure while maintaining efficient processing.

Inventive Principle:
Principle #1Segmentation

3Reliability

If dopants are introduced without precise control, then the process is simpler, but access resistance increases

Engineering Contradiction:
Improvedevice performanceVSAvoiddoping process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The sacrificial layers and spacers serve as intermediary structures that enable precise dopant placement. These intermediaries guide the doping process to specific locations, ensuring that dopants are introduced exactly where needed to optimize electrical contacts. This indirect control through intermediary structures reduces access resistance by ensuring proper dopant positioning without requiring complex direct manipulation techniques.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Reliability

If dopant placement is not precisely controlled, then manufacturing is easier, but device performance variability increases

Engineering Contradiction:
Improveperformance consistencyVSAvoiddopant placement control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent uses preliminary action by establishing the sacrificial layer and spacer structure before doping. This preparatory framework pre-defines the exact locations and dimensions where dopants will be placed, ensuring consistent dopant positioning across all devices. The preliminary structure acts as a template that guarantees repeatable dopant placement, reducing performance variability without requiring complex real-time adjustments during doping.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables precise control over dopant placement, achieving a uniform junction along the fin length, optimizing device performance, and reducing variability while minimizing dopant presence in the channel.

Implementation Method 1

growing semiconductor material in the recesses

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Implementation Method 2

in-situ doped selective epitaxy to form a quasi uniform bottom plate

Methodology Applied
Scientific EffectIn-situ doped selective epitaxy: Epitaxy

Data Source

PatentUS10141446B2Formation of bottom junction in vertical FET devices
Publication Date: 2018.11.27 GLOBALFOUNDRIES US INC
  • US10141446B2 patent drawing
  • US10141446B2 patent drawing
  • US10141446B2 patent drawing

AI summary

Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.