Vertical-Transport FET Bottom Source Layout for Lower Parasitics

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Solution Overview

Problem

The challenge in integrated circuit fabrication lies in achieving high transistor density and performance while minimizing parasitic resistance and capacitance, particularly in vertical-transport field effect transistors (FETs), where conventional top-sided contacts lead to trade-offs between contact resistance and capacitance, and the scaling of multi-gate and nanowire transistors faces constraints in lithographic processes.

Innovation Solution

The implementation of vertical-transport FETs with a bottom source connection through a backside power delivery scheme, utilizing conductive deep via structures and buried power rails to reduce parasitic resistance and capacitance, allowing for increased transistor density and improved performance by decoupling via sizes from device pitch and enabling more aggressive diffusion-to-diffusion spacing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If top-sided contacts are used in vertical-transport FETs, then device fabrication is simplified, but parasitic resistance and capacitance increase

Engineering Contradiction:

Improvedevice fabrication simplicityVSAvoidparasitic resistance and capacitance

Core Design Contradiction:

Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent inverts the conventional contact arrangement by moving the source contact from the top side to the bottom side of the vertical-transport FET. This inversion allows the source contact to be formed simultaneously with the substrate contact during the same lithographic step, eliminating the need for separate contact holes and reducing parasitic resistance and capacitance while simplifying the fabrication process

Inventive Principle:

Principle #13The other way round (Inversion)

2Productivity

If transistor dimensions are scaled down to increase density, then more devices fit on chip, but lithographic process constraints become overwhelming

Engineering Contradiction:

Improvetransistor densityVSAvoidlithographic process constraints

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the source contact formation with the substrate contact formation by positioning both contacts at the bottom side of the device. This allows both contacts to be patterned in the same lithographic step using a single mask, effectively combining two separate lithographic operations into one, thereby reducing process complexity and enabling further scaling

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from a planar contact arrangement to a vertical arrangement by placing contacts at the bottom side of the vertical-transport FET. This dimensional change allows contacts to be formed outside the active device footprint, enabling more aggressive diffusion-to-diffusion spacing and higher transistor density without increasing lithographic complexity

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If conventional top-sided contacts are used, then contact formation is straightforward, but contact resistance and capacitance trade-offs limit performance

Engineering Contradiction:

Improvecontact formation simplicityVSAvoidcontact resistance and capacitance performance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent inverts the contact location from top-sided to bottom-sided, allowing the source contact to be formed in the same lithographic step as the substrate contact. This inversion eliminates the need for separate contact holes through the device stack, reducing both parasitic resistance and capacitance while maintaining fabrication simplicity

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent introduces a bottom contact structure that serves as an intermediary connection point for both the source and substrate. This bottom contact arrangement acts as a mediator that reduces the parasitic elements by providing direct electrical paths without requiring additional contact holes through the device stack, thereby improving performance

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20250006837A1Integrated circuit structures having vertical-transport transistor with bottom source connection

Publication Date: 2025.01.02 INTEL CORP

AI summary

Structures having vertical-transport field effect transistors (FETs) with bottom source connection are described. In an example, an integrated circuit structure includes a channel structure above a substrate. A gate structure is laterally surrounding the channel structure. A drain structure is above the gate structure and on the channel structure. A metal source structure is below the substrate and vertically beneath the channel structure. A conductive via is through the substrate, the conductive via coupling the metal source structure to the channel structure.