Vertical FET Bottom Source-Drain Formation via Sacrificial Layer
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Solution Overview
Problem
Conventional field-effect transistors (FETs) face challenges in high power applications due to complex metallization patterns required for parallel connections, and in vertical FETs, precise control of the channel layer etching is difficult, leading to varying gate-to-channel alignment issues.
Innovation Solution
A method for forming a bottom source-drain layer in vertical FETs involves creating an anchor structure on a substrate with a sacrificial layer and channel layer, patterning vertical fins, and removing the sacrificial layer to form floating fins with a gap, which is then filled by the bottom source-drain layer, allowing for improved control over the source-drain height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional FETs are connected in parallel for high power capability, then power capability is improved, but metallization pattern complexity increases
Solution Approach 1:
The patent transitions from planar FET architecture to vertical FET architecture, moving the current flow from the plane of the substrate to the vertical dimension. This dimensional change allows source-drain current to flow perpendicular to the substrate surface, eliminating the need for complex surface metallization patterns while maintaining high power capability through parallel vertical device connections
2Device complexity
If vertical FETs are used to simplify metallization, then device complexity is reduced, but channel layer etching precision control becomes difficult
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary between the substrate and the channel layer. This sacrificial layer serves as a placeholder during fabrication that defines the precise position where the bottom source-drain layer will eventually form. By using this intermediary structure, the patent achieves precise control over channel layer etching and gate-to-channel alignment that would otherwise be difficult in vertical FET fabrication
3Manufacturing precision
If sacrificial layer is removed to form floating fins, then bottom source-drain height control is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent employs preliminary action by depositing the sacrificial layer before forming the channel layer and vertical fins. This sacrificial layer pre-defines the exact location and depth where the bottom source-drain layer will be formed after sacrificial layer removal. The preliminary placement of this sacrificial structure enables precise height control of the bottom source-drain layer, as its removal creates a controlled cavity that guides subsequent material deposition
Data Source
AI summary
In an embodiment, this invention relates to a vertical field-effect transistor component including a bottom source-drain layer and a method of creating the same. The method of forming a bottom source-drain layer of a vertical field-effect transistor component can comprise forming an anchor structure on a substrate. A sacrificial layer can be deposited on a middle region of the substrate and a channel layer can be deposited on the sacrificial layer. A plurality of vertical fins can be formed on the substrate and the sacrificial layer can be removed such that the plurality of vertical fins in the middle region form a plurality of floating fins having a gap located between the plurality of floating fins and the substrate. The bottom source-drain layer can then be formed such that the bottom source-drain layer fills in the gap.