Vertical FET High Density Capacitor Gate Stack Optimization
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Solution Overview
Problem
Current semiconductor technologies face challenges in integrating high density capacitors with minimal process complexity and low leakage into advanced nodes, particularly in vertical field effect transistors.
Innovation Solution
The integration of high density capacitors is achieved by extending the gate length in the capacitor during the fabrication process of vertical transistors, using a similar production flow, which involves forming a bottom terminal and channel region for both the transistor and capacitor, depositing spacers, dielectric, and gate materials, and optimizing the gate stack heights to maximize capacitance while minimizing process changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high density capacitors are integrated into advanced nodes, then capacitance density is improved, but process complexity increases
Solution Approach 1:
The patent merges the capacitor fabrication process with the existing vertical transistor production flow. Both devices share common process steps including forming bottom terminals, depositing spacers, and creating gate stacks. This integration allows high density capacitors to be manufactured alongside transistors using the same process infrastructure, thereby increasing capacitance density without proportionally increasing process complexity
Solution Approach 2:
The patent creates a universal fabrication process that can produce both vertical transistors and high density capacitors. The same deposition, etching, and doping processes are used for both device types, with the capacitor structure being a variant of the transistor fabrication sequence. This multi-functional approach enables the manufacturing system to produce different device types with minimal additional complexity
2Quantity of substance
If gate stack height is increased to maximize capacitance, then capacitance density is improved, but leakage increases
Solution Approach 1:
The patent applies different local qualities to different regions of the device. The capacitor region features a taller gate stack for maximum capacitance, while the transistor region maintains the original gate stack height. The spacer material is selectively removed in the capacitor region but retained in the transistor region, creating locally optimized structures that achieve high capacitance density without compromising transistor performance or introducing excessive leakage
Solution Approach 2:
The patent uses the transistor fabrication process as a template or copy for creating the capacitor structure. The capacitor is essentially a modified version of the transistor process where the spacer is removed and the gate stack is extended. This copying approach allows the proven transistor process to be replicated for capacitors with minimal modifications, achieving high capacitance while maintaining process control to prevent leakage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in high density capacitors with minimal additional process complexity, delivering maximum capacitance and low leakage, effectively addressing the need for advanced node requirements.
Implementation Method 1
The applied gate voltage imposes an electric field into the device, which in turn attracts or repels charge carriers to or from the region between a source terminal and a drain terminal
Implementation Method 2
contain at least two electrical conductors (plates) separated by a dielectric (i.e., an insulator that can store energy by becoming polarized)
Data Source
AI summary
A technique relates to semiconductors. A bottom terminal of a transistor and bottom plate of a capacitor are positioned on the substrate. A spacer is arranged on the bottom terminal of the transistor. A transistor channel region extends vertically from the bottom terminal through the spacer to contact a top terminal of the transistor. A capacitor channel region extends vertically from the bottom plate to contact a top plate of the capacitor. A first gate stack is arranged along sidewalls of the transistor channel region and is in contact with the spacer. A second gate stack is arranged along sidewalls of the capacitor channel region and is disposed on the bottom plate. A distance from a bottom of the first gate stack to a top of the bottom terminal is greater than a distance from a bottom of the second gate stack to a top of the bottom plate.