Vertical Channel FET Structure for Lower Contact Resistance and Capacitance
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Solution Overview
Problem
As electronic devices become more complex and require smaller IC chips, the miniaturization of transistors leads to short channel effects (SCEs) such as increased current leakage and reduced threshold voltage in planar transistors, degrading performance.
Innovation Solution
The development of vertical channel field-effect transistors (VCFETs) with a semiconductor channel extending vertically, featuring an expanded end portion to reduce contact resistance and the use of air gaps in spacers to decrease parasitic capacitance, allowing for better electrostatic control and higher current density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the channel length is reduced in planar transistors to increase drive strength, then the parasitic capacitance is reduced and drive strength increases, but short channel effects occur causing current leakage and threshold voltage degradation
Solution Approach 1:
The patent transitions from planar transistors to vertical channel field-effect transistors (VCFETs), changing the channel orientation from horizontal to vertical. This dimensional change allows the channel to extend in the vertical direction while maintaining a larger effective channel length, thereby reducing short channel effects and improving threshold voltage stability without sacrificing drive strength.
Solution Approach 2:
The patent implements an all-around gate structure that completely surrounds the vertical channel, with the gate wrapped around the channel in multiple directions. This nested configuration provides superior electrostatic control over the channel, effectively suppressing short channel effects and maintaining stable threshold voltage while enabling compact device footprint.
2Area of stationary object
If the vertical channel is elongated to conserve area and improve electrostatic control, then the area is reduced and electrostatic control is improved, but the contact area is reduced increasing parasitic contact resistance
Solution Approach 1:
The patent introduces expanded end portions at the top and bottom of the vertical channel, creating horizontal expansion zones. This allows the contact area to be increased in the horizontal plane without increasing the overall vertical channel length, thereby reducing parasitic contact resistance while maintaining compact device footprint.
Solution Approach 2:
The patent applies local geometric modification by expanding only the end portions of the vertical channel where contacts are formed, while keeping the main channel body narrow. This localized expansion increases contact area specifically where needed without affecting the electrostatic control or increasing the overall device area.
3Power
If more gate material is added around the vertical channel to improve electrostatic control, then the electrostatic control and current capacity are improved, but the parasitic capacitance between gate and contact increases
Solution Approach 1:
The patent removes or reduces the dielectric material in the spacer regions between the gate and the contacts, creating air gaps. This extraction of dielectric material reduces the parasitic capacitance between the gate and contacts, counteracting the capacitance increase from the all-around gate structure.
Solution Approach 2:
The patent introduces air gaps within the spacer structure, creating a porous or hollow configuration. Air has much lower permittivity than solid dielectric materials, so these air-filled spaces significantly reduce the parasitic capacitance between the gate and contacts while maintaining the electrostatic control benefits of the all-around gate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
VCFETs provide reduced contact resistance and parasitic capacitance, enhancing performance by conserving area and improving charge transport efficiency, thus addressing the limitations of miniaturized transistors.
Implementation Method 1
A parasitic capacitance exists between the gate and the contact when an energy is applied to the gate of the VCFET to create an electric field in the vertical channel. Reducing the permittivity of the spacer between the gate and the contact reduces the parasitic capacitance of the VCFET.
Implementation Method 2
The vertical channel of the VCFET is configured to transport charge in a vertical direction orthogonal to the substrate along the height of the vertical channel between the source and the drain in response to an electric field created by energy applied to a gate
Data Source
AI summary
Vertical channel field-effect transistors (VCFETs) with reduced contact resistance and/or parasitic capacitance, and related fabrication methods. In exemplary aspects, to reduce contact resistance of the VCFET, an end portion of the vertical channel has a semiconductor structure that has an expanded width in the horizontal direction parallel to the substrate surface. This provides a greater area to form a contact for a source/drain to reduce contact resistance of the VCFET. To reduce the parasitic capacitance between the gate and a contact of the VCFET, the spacer includes one or more air gaps that form an air spacer(s) between the gate and the contact to reduce the overall average permittivity of the spacer. In one example, the air spacer(s) of the VCFET is elongated in the horizontal direction parallel to the substrate surface (and perpendicular to the vertical direction of the vertical channel) to further reduce the parasitic capacitance.