Vertical FET Critical Dimension Control via Epitaxial Layer Stacking
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Solution Overview
Problem
Current methods for forming vertical field effect transistors (VFETs) face challenges in critical dimension control, leading to variations in gate length and alignment of junction doping, which result in performance issues such as variations in threshold voltage.
Innovation Solution
A method involving epitaxial deposition of five semiconductor layers on a substrate, where the stack is patterned into fins, and vertical surfaces are selectively etched to form spacer and gate cavities, allowing for precise control of spacer and gate lengths by filling these cavities with spacers and a gate structure, respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current techniques are used to form VFETs, then device density can be increased, but critical dimension control becomes challenging resulting in performance variations
Solution Approach 1:
The patent applies preliminary action by forming spacer cavities and gate cavities through selective etching of semiconductor layers before depositing the spacer and gate materials. This pre-defined cavity structure ensures that the final spacer and gate dimensions are determined by the cavity heights, which are controlled during the layer formation process, rather than relying on post-deposition etching that introduces variability.
Solution Approach 2:
The patent replaces traditional mechanical dimension control methods (such as timed etching) with a deposition-based approach. By forming cavities with specific heights and then filling them with materials, the dimensional control transitions from being limited by etch rate variations to being controlled by deposition thickness, which can be more precisely controlled.
2Manufacturing precision
If gate length and alignment are not precisely controlled, then manufacturing is simpler, but threshold voltage variations occur
Solution Approach 1:
The patent applies self-service through self-aligned processes where the spacer cavities and gate cavities are formed by selectively etching specific semiconductor layers that are already positioned relative to each other. The subsequent spacer and gate deposits automatically align with these pre-formed cavities, eliminating the need for separate alignment steps and ensuring precise gate length and positioning without additional complexity.
3Manufacturing precision
If selective etching is used to form cavities, then spacer and gate lengths can be precisely controlled, but process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the fin structure into multiple semiconductor layers with different materials that can be selectively etched. By segmenting the structure into distinct layers (such as silicon germanium and silicon layers), the process enables selective removal of specific layers to form cavities while preserving others, achieving precise dimensional control through material segmentation rather than complex process sequencing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control of critical dimensions, reducing performance variations and improving the reliability of VFETs by ensuring consistent spacer and gate lengths, thereby enhancing the accuracy of device fabrication.
Implementation Method 1
epitaxial deposition can be used to form five semiconductor layers in a stack on a semiconductor substrate
Implementation Method 2
vertical surfaces of the second and fourth semiconductor layers of the fin(s) can be selectively etched back to form upper and lower spacer cavities
Data Source
AI summary
Disclosed are a method of forming vertical field effect transistor(s) and the resulting structure. In the method, five semiconductor layers are formed in a stack by epitaxial deposition. The first and fifth layers are one semiconductor material, the second and fourth layers are another and the third layer is yet another. The stack is patterned into fin(s). Vertical surfaces of the second and fourth layers of the fin(s) are etched to form upper and lower spacer cavities and these cavities are filled with upper and lower spacers. Vertical surfaces of the third layer of the fin(s) are etched to form a gate cavity and this cavity is filled with a gate. Since epitaxial deposition is used to form the semiconductor layers, the thicknesses of these layers and thereby the heights of the spacer cavities and gate cavity and the corresponding lengths of the spacers and gate can be precisely controlled.