Vertical Field Effect Transistor Fabrication Using Directional Doping
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Solution Overview
Problem
Current transistor fabrication processes face challenges in achieving uniformity and efficiency in forming vertical field effect transistors, particularly in controlling the channel length and material uniformity for high-density integrated circuit applications.
Innovation Solution
A method for fabricating a vertical field effect transistor involves forming a fin structure with vertically stacked spacers and a gate pattern, using directional doping and planarization processes to create doped and undoped regions, and forming a filler pattern to ensure uniform channel length and material distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional transistor fabrication processes are used, then manufacturing simplicity is maintained, but manufacturing precision of channel length and material uniformity deteriorates
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming preliminary spacers, performing selective directional doping to create doped and undoped regions, removing undoped regions, and forming gate patterns. Each segment addresses specific precision requirements independently, allowing cumulative achievement of overall channel length uniformity without requiring complete process redesign.
Solution Approach 2:
Different regions of the preliminary spacer layer are doped with different concentrations or types of impurities through directional doping processes. The undoped regions are selectively removed to create trenches, while doped regions remain to form the lower spacers. This local differentiation enables precise control of electrical properties and physical dimensions in specific areas, achieving superior manufacturing precision in critical channel length regions.
2Manufacturing precision
If directional doping and planarization processes are used, then material uniformity is improved, but manufacturing time increases
Solution Approach 1:
The preliminary spacer layer is formed and doped before the gate pattern is created. This preliminary doping action establishes the electrical and physical properties of the lower spacer regions in advance, allowing subsequent gate formation and upper spacer creation to proceed without additional doping steps. The planarization process is also performed at strategic intermediate stages to prepare surfaces for subsequent deposition, reducing the need for re-work and minimizing total fabrication time while maintaining material uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of transistors with uniform channel lengths and improved material distribution, enhancing the performance and efficiency of vertical field effect transistors for high-density integrated circuits.
Implementation Method 1
a doped region and an undoped region are formed in the preliminary spacer layer by doping partially impurities in the preliminary spacer layer using a directional doping process
Implementation Method 2
The upper doped region is removed using a planarization process
Implementation Method 3
The undoped region is removed using an isotropic etching process
Data Source
AI summary
The present invention concept relates to vertical field effect transistor and method of fabricating the same. A method of fabricating a vertical field effect transistor is provided as follows. A fin structure having a sidewall is formed on a substrate. A lower spacer, a gate pattern and an upper spacer surround a lower sidewall region, a center sidewall region and an upper sidewall region, respectively. The lower spacer, the gate pattern and the upper spacer are vertically stacked on each other along the sidewall of the fin structure. To form the lower spacer, a preliminary spacer layer is formed to surround the lower sidewall region of the fin structure; a doped region and an undoped region are formed in the preliminary spacer layer by doping partially impurities in the preliminary spacer using a directional doping process; and the undoped region of the preliminary spacer layer is removed so that the doped region of the preliminary spacer layer remains to form the lower spacer.