Self-Aligned Drain Spacer in Vertical FETs via Angled Ion Implant

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Solution Overview

Problem

Conventional vertical FET patterning techniques face challenges with precise alignment of contacts, gates, sources, drains, and junctions, leading to misalignment errors and reduced device reliability.

Innovation Solution

An angled ion implant method is used to form a drain in the upper section of pillars in a vertical field-effect transistor (vFET) while modifying the capping layer to create a hardened spacer, which remains self-aligned after etching the lower section, reducing misalignment and improving device reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional vFET patterning techniques are used, then vertical FETs can be formed with channels perpendicular to the substrate surface, but precise alignment of contacts, gates, sources, drains, and junctions becomes difficult leading to misalignment errors

Engineering Contradiction:
Improvealignment precisionVSAvoiddevice reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The capping layer is formed over the pillars before the angled ion implant process. This preliminary action creates a protective and defining structure that guides the subsequent drain formation process, ensuring the drain is self-aligned to the pillar top surface without requiring additional alignment steps

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The angled ion implant process automatically forms the drain junction self-aligned to the pillar top surface. The geometry of the angled implant combined with the capping layer configuration causes the drain to form precisely where needed without external alignment control, making the structure self-aligning

Inventive Principle:
Principle #25Self-service

2Reliability

If the capping layer is removed completely to access the pillar, then subsequent processing can be performed, but the drain junction cannot be self-aligned to the spacer or cap at the top of the vFET

Engineering Contradiction:
Improvedevice reliabilityVSAvoidalignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The capping layer is selectively removed only from the lower section of the pillars while maintaining it at the upper section where the drain junction forms. This local differentiation allows the capping layer to serve dual purposes: protecting the structure during processing and defining the drain alignment position

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The selective removal of the capping layer is performed in advance of the drain formation process. By removing the capping layer from the lower section while preserving it at the upper section beforehand, the structure is prepared to receive the angled ion implant that will form the self-aligned drain junction

Inventive Principle:
Principle #10Preliminary action

3Reliability

If conventional patterning techniques are used, then all components can be formed, but gate-to-drain parasitic capacitance increases due to misalignment

Engineering Contradiction:
Improvedevice reliabilityVSAvoidgate-to-drain parasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The angled ion implant process with the capping layer configuration causes the drain junction to form automatically in the correct position relative to the gate and other structures. This self-alignment eliminates parasitic capacitance issues that would otherwise require complex alignment control

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The angled ion implant method effectively self-aligns the drain junction to the spacer, enhancing device reliability by reducing gate-to-drain parasitic capacitance and improving packing density through precise positioning.

Implementation Method 1

forming a drain in an upper section of each of the plurality of pillars by performing an angled implant to each of the plurality of pillars. The angled implant may be delivered at a non-zero angle of inclination relative to a perpendicular extending from a top surface of the base layer

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS11640987B2Implant to form vertical FETs with self-aligned drain spacer and junction
Publication Date: 2023.05.02 APPLIED MATERIALS INC
  • US11640987B2 patent drawing
  • US11640987B2 patent drawing
  • US11640987B2 patent drawing

AI summary

Disclosed herein are methods for forming vertical field-effect-transistor (vFET). In some embodiments, a method includes providing a device structure including a plurality of pillars extending from a base layer, forming a capping layer over the device structure, and forming a drain in an upper section of each of the plurality of pillars by performing an angled implant to each of the plurality of pillars. The angled implant may be delivered at a non-zero angle of inclination relative to a perpendicular extending from a top surface of the base layer. The method may further include etching the device structure to remove the capping layer from along a lower section of each of the plurality of pillars, wherein the capping layer remains along the upper section of each of the plurality of pillars.