Monolithic Power FET and Lateral Gate Driver Integration for Lower Loss
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Solution Overview
Problem
Existing power electronic circuits for power control applications, such as half-bridge circuits, require reduction in size and efficiency due to the separate packaging of power MOSFETs and gate drivers, leading to increased size and losses in circuits like multichip modules.
Innovation Solution
A semiconductor device with a vertically integrated power FET and laterally integrated FETs, where the lateral FETs form part of the gate driver circuit, monolithically integrated into a common semiconductor substrate, reducing physical size and electrical connection lengths, and enhancing efficiency by integrating driver devices within the power MOSFET die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate packaged components are used for power MOSFET and gate driver, then ease of manufacture is improved, but device size increases and electrical losses increase
Solution Approach 1:
The patent merges the power MOSFET and gate driver circuitry into a single monolithic semiconductor device. The gate driver transistors (first and second lateral FETs) and the power MOSFET are integrated on the same semiconductor substrate, eliminating the need for separate packaged components and reducing overall circuit size.
Solution Approach 2:
The semiconductor substrate serves multiple functions simultaneously: it hosts the power MOSFET for power switching, the lateral FETs for gate driving, and provides electrical interconnections. This multi-functional integration reduces the number of discrete components needed.
2Ease of manufacture
If separate packaged components are used for power MOSFET and gate driver, then ease of manufacture is improved, but electrical losses increase
Solution Approach 1:
By combining the gate driver and power MOSFET into one device, the patent eliminates external electrical connections between separate components. The monolithic integration removes interface losses and reduces parasitic inductance and resistance associated with inter-component bonding wires and traces.
3Volume of moving object
If monolithic integration is implemented, then circuit size is reduced and electrical losses are reduced, but device complexity increases
Solution Approach 1:
The monolithic device is segmented into distinct functional regions: the power MOSFET section with its source, drain, and gate, and the gate driver section with the lateral FETs. This segmentation allows each component to be optimized independently while maintaining overall integration benefits.
Solution Approach 2:
Different regions of the semiconductor substrate are assigned different doping types and structures tailored to specific functions. The power MOSFET region uses vertical channel structures optimized for high current, while the gate driver region uses lateral FET structures with appropriate doping for switching control.
Data Source
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AI summary
In an embodiment, a semiconductor device is provided that comprises a vertical power FET (15, 16) for switching a load current, the power FET having a channel region formed by charge carriers of a first conductivity type and a first lateral FET (17) and a second lateral FET (18) providing an output stage (19) of gate driver circuitry (10) for driving the power FET, wherein the first lateral FET has a channel region formed by charge carriers of the first conductivity type and the second lateral FET has a channel region formed by charge carriers of a second conductivity type opposing the first conductivity type. The power FET and the first and second lateral FETs are monolithically integrated into a semiconductor substrate of the first conductivity type that comprises a first surface and a drain of the first lateral FET and a source of the second lateral FET are electrically coupled to a gate of the power FET.