Vertical Power FET and Lateral Gate Driver Integration for Lower Loss

Solution Overview

Problem

Existing power electronic circuits for power control applications are large in size due to separate packaging of power MOSFETs and gate drivers, leading to increased size and losses in circuits.

Innovation Solution

A semiconductor device with a vertically integrated power FET and a laterally integrated FET, where the lateral FET forms part of the gate driver circuit and is monolithically integrated with the vertical power FET in a common semiconductor substrate, reducing physical size and electrical connection length, thereby reducing losses and improving efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If separate packaged components are used for power MOSFET and gate driver, then ease of manufacture is improved, but device size increases and efficiency decreases

Engineering Contradiction:

Improveease of manufactureVSAvoidcircuit size

Core Design Contradiction:

Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent merges the power MOSFET and gate driver into a single monolithic integrated circuit on one semiconductor substrate. The driver circuit is formed in a first region of the substrate while the power MOSFET is formed in a second region, with direct electrical connection between them, eliminating the need for separate packages and reducing overall circuit size.

Inventive Principle:

Principle #5Merging (Combining)

2Ease of manufacture

If separate packaged components are used for power MOSFET and gate driver, then ease of manufacture is improved, but energy losses increase due to longer electrical connections

Engineering Contradiction:

Improveease of manufactureVSAvoidenergy losses

Core Design Contradiction:

Ease of manufactureVSLoss of energy

Solution Approach 1:

The patent merges the power MOSFET and gate driver into a single monolithic integrated circuit on one semiconductor substrate. The driver circuit is formed in a first region of the substrate while the power MOSFET is formed in a second region, with direct electrical connection between them, eliminating the need for separate packages and reducing overall circuit size.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentEP4250347A1Semiconductor device and method of fabricating a semiconductor device

Publication Date: 2023.09.27 INFINEON TECH AUSTRIA AG

Figure 1
Figure 2
Figure 3

AI summary

In an embodiment, a semiconductor device (1000) is provided that comprises a vertical power FET (21) for switching a load current, the vertical power FET (21) having a channel formed by charge carriers of a first conductivity type and a lateral FET (22) for driving the vertical power FET, the lateral FET (22) having a channel formed by charge carriers of a second conductivity type opposing the first conductivity type. The vertical power FET (21) and the lateral FET (22) are monolithically integrated into a semiconductor substrate (20) of the first conductivity type and a drain (25) of the lateral FET (22) is electrically coupled to a gate (26) of the vertical power FET (21).