Self-Aligned Gate Contacts in Vertical FETs
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Solution Overview
Problem
The increased packing density of vertical FETs leads to challenges in forming contacts to the gate, source, and drain, resulting in misalignment errors and undesirable electrical coupling, particularly at fin pitches of 36 nm or less, which can cause short circuits and reduce the effectiveness of the vFETs.
Innovation Solution
A method for forming self-aligned gate contacts in vertical FETs by depositing a mask over the semiconductor device, forming a gate contact opening only over the second portion of the gate, and filling it with a gate contact material, while ensuring the top surface of the first portion of the gate is higher than the top source/drain region, reducing the risk of misalignment and electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional patterning techniques are used to form contacts in densely packed vFETs, then contact formation is achieved, but misalignment errors occur and electrical coupling between contacts increases
Solution Approach 1:
The gate structure serves itself as the alignment reference for contact formation. The self-aligned process uses the gate's own geometry (particularly the elevated second portion) to define the contact opening position, eliminating the need for separate alignment steps and reducing misalignment errors while preventing electrical coupling between adjacent contacts
Solution Approach 2:
The invention introduces vertical dimensionality by creating a gate with a second portion that extends higher than the top source/drain region. This vertical extension provides a unique alignment reference that prevents horizontal misalignment and electrical coupling, adding a Z-dimension solution to an XY-plane problem
2Productivity
If fin pitch is reduced to increase packing density, then device density increases, but misalignment errors and electrical coupling between contacts worsen
Solution Approach 1:
The gate structure serves itself as the alignment reference for contact formation. The self-aligned process uses the gate's own geometry (particularly the elevated second portion) to define the contact opening position, eliminating the need for separate alignment steps and reducing misalignment errors while preventing electrical coupling between adjacent contacts
Solution Approach 2:
The invention introduces vertical dimensionality by creating a gate with a second portion that extends higher than the top source/drain region. This vertical extension provides a unique alignment reference that prevents horizontal misalignment and electrical coupling, adding a Z-dimension solution to an XY-plane problem
3Ease of manufacture
If contact opening dimensions are increased to facilitate formation, then contact formation becomes easier, but misalignment and electrical coupling between contacts increase
Solution Approach 1:
The gate structure serves itself as the alignment reference for contact formation. The self-aligned process uses the gate's own geometry (particularly the elevated second portion) to define the contact opening position, eliminating the need for separate alignment steps and reducing misalignment errors while preventing electrical coupling between adjacent contacts
Solution Approach 2:
The invention introduces vertical dimensionality by creating a gate with a second portion that extends higher than the top source/drain region. This vertical extension provides a unique alignment reference that prevents horizontal misalignment and electrical coupling, adding a Z-dimension solution to an XY-plane problem
Data Source
AI summary
A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor including a gate contact patterned in a self-aligned process. In one embodiment, we disclose a semiconductor device, including a semiconductor substrate and a first vertical field effect transistor (vFET) including a bottom source/drain (S/D) region disposed on the semiconductor substrate; a fin disposed above the bottom S/D region; a top source/drain (S/D) region disposed above the fin and having a top surface; and a gate having a top surface higher than the top surface of the top S/D region. A gate contact may be formed over the gate.