Vertical FET Gate Structure with Non-Uniform Dielectric Thickness
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Solution Overview
Problem
Existing vertical field effect transistor (VFET) technologies face challenges in forming an effective gate structure that maintains performance due to issues with gate dielectric layer thickness and conductor layer alignment, leading to potential performance degradation.
Innovation Solution
The proposed VFET device includes a fin structure with a gate dielectric layer and a conductor layer, where the gate dielectric layer is formed on the sidewall of the fin, and a top spacer is created between the top source/drain region and the conductor layer, with the gate dielectric layer's top surface positioned at the same or lower height than the top spacer, preventing performance degradation by managing equivalent oxide thickness (EOT) increases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate dielectric layer is formed thicker to prevent leakage, then reliability is improved, but equivalent oxide thickness increases leading to performance degradation
Solution Approach 1:
The patent transitions from controlling gate dielectric thickness in a single lateral dimension to managing it across multiple vertical levels. The gate dielectric layer is formed with different thicknesses at different heights: a first thickness at the lower level and a second (thinner) thickness at the upper level, where the top surface of the gate dielectric layer is positioned at the same or lower height than the top surface of the top spacer. This vertical dimensionality allows preventing leakage while maintaining effective gate control.
Solution Approach 2:
The gate dielectric layer is designed with non-uniform thickness distribution: thicker regions at the lower portion for leakage prevention and thinner regions at the upper portion for maintaining equivalent oxide thickness. The top surface of the gate dielectric layer is positioned at the same or lower height than the top surface of the top spacer, creating localized thickness variations that simultaneously address both reliability and performance requirements.
2Manufacturing precision
If the gate structure is made more complex to improve performance, then VFET performance is improved, but device complexity increases
Solution Approach 1:
The gate structure is segmented into distinct functional components: a gate dielectric layer with varying thickness, a conductor layer, a top spacer, and a bottom spacer. Each component serves a specific function - the gate dielectric layer for electrical isolation and field control, the conductor layer for gate electrode function, and the spacers for structural support and alignment. This segmentation allows complex performance optimization while maintaining manufacturing feasibility through modular construction.
Solution Approach 2:
The gate structure employs a nested configuration where the gate dielectric layer is positioned on the sidewall of the fin structure, the conductor layer is formed on the gate dielectric layer, and the top spacer is formed on the upper portion of the gate dielectric layer. This nested arrangement integrates multiple functional layers in a compact vertical stack, improving performance without proportionally increasing horizontal device footprint.
3Ease of manufacture
If the top surface of the gate dielectric layer is positioned higher than the top surface of the conductor layer, then manufacturing is simplified, but performance degradation occurs due to EOT increases
Solution Approach 1:
The patent specifies that the top surface of the gate dielectric layer be positioned at the same or lower height than the top surface of the top spacer, and higher than the top surface of the conductor layer. This preliminary positioning establishes the correct vertical hierarchy before subsequent manufacturing steps, ensuring that the gate dielectric layer maintains appropriate thickness relationships with other components, thereby preventing equivalent oxide thickness increases and performance degradation.
Data Source
AI summary
A vertical field-effect transistor (VFET) includes: a fin structure on a substrate; a gate structure including a gate dielectric layer on an upper portion of a sidewall of the fin structure, and a conductor layer on a lower portion of the gate dielectric layer; a top source/drain (S/D) region above the fin structure and the gate structure; a bottom S/D region below the fin structure and the gate structure; a top spacer on an upper portion of the gate dielectric layer, and between the top S/D region and a top surface of the conductor layer; and a bottom spacer between the gate structure and the bottom S/D region. A top surface of the gate dielectric layer is positioned at the same or substantially same height as or positioned lower than a top surface of the top spacer, and higher than the top surface of the conductor layer.