Vertical FET Gate Length Control via Mask-Defined Fin Trimming
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Solution Overview
Problem
The manufacture of vertical Field-Effect Transistors (FETs) faces challenges such as defectivity risks in finned epitaxy, complexity in forming thick and thin gate dielectric devices, and difficulty in controlling gate length, particularly due to the need for precise integration techniques that compromise gate resistance and increase manufacturing complexity.
Innovation Solution
A method involving the growth of a bottom source-drain layer and a channel layer on a substrate, followed by forming fins with a wider mask, trimming them to a predetermined width, and forming a high-k dielectric and metal gate layer, where the mask defines the gate top edge, allowing for efficient gate length control and reduced defectivity through chemical metal polishing and conformal deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the finned channel region is formed by growth inside a confined cavity, then the fin region can be formed with precise geometry, but defectivity risk increases at the interface between the finned epitaxy region and the bottom source/drain region
Solution Approach 1:
The patent forms the bottom source/drain region and its spacer before forming the finned channel region. This preliminary action allows the fin epitaxy to grow on a pre-formed, stable substrate without interface defects, while the pre-formed spacer defines the final fin geometry and gate length without requiring post-formation adjustments
2Manufacturing precision
If additional gate etching is performed to control gate length, then gate length can be adjusted, but gate resistance increases and epitaxial growth defects occur
Solution Approach 1:
The bottom source/drain spacer is formed beforehand with a width that directly defines the gate length. This preliminary dimensioning eliminates the need for subsequent gate etching to control gate length, thereby avoiding increased gate resistance and epitaxial growth defects that would result from additional etching steps
Solution Approach 2:
The bottom source/drain spacer acts as an intermediary element that indirectly defines the gate length. Instead of directly etching the gate to control its length, the spacer serves as a template that determines the gate length through conformal deposition, avoiding direct gate modification and associated defects
3Adaptability or versatility
If thick gate dielectric and thin gate dielectric devices are formed on the same chip, then device versatility is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies different gate dielectric thicknesses to different regions of the chip by performing selective removal of the gate dielectric. This local modification allows some devices to have thick gate dielectric while others have thin gate dielectric, enabling device versatility without requiring completely separate manufacturing processes for each device type
4Ease of manufacture
If the mask width is wider than the final fin width, then gate length control is simplified, but additional trimming steps are required
Solution Approach 1:
The bottom source/drain spacer serves as an intermediary that transfers the dimensioning function from the mask to the final gate structure. The mask can be wider than the final fin width because the spacer, formed conformally on the bottom source/drain region, defines the critical dimensions. This intermediary approach simplifies gate length control while the trimming step becomes a routine part of the process rather than a complex operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient gate length control and reduces manufacturing complexity by minimizing defectivity risks and simplifying the formation of both long and short channel devices in vertical FETs, improving the overall manufacturing process.
Implementation Method 1
The bottom source-drain layer and the top source-drain epitaxial layer are highly doped of the second type compared to the doping of the substrate of the first type
Implementation Method 2
performing chemical metal polishing to the mask
Implementation Method 3
forming a high-k dielectric layer on the bottom spacer, first fin, and the mask, forming and metal gate layer on the high-k dielectric layer
Implementation Method 4
forming a top spacer by conformal deposition and directional etch back to form a recessed area
Implementation Method 5
growing a top source-drain epitaxial layer of a second type on the first fin and the top spacer
Data Source
AI summary
A semiconductor structure and a method a method of forming a vertical FET (Field-Effect Transistor), includes growing a bottom source-drain layer of a second type on a substrate of a first type, growing a channel layer on the bottom source-drain layer, forming a first fin from the channel layer with mask on top of the first fin. A width of the mask is wider than a final first fin width.