Vertical FET Gate Pitch Scaling via End Contacts
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Solution Overview
Problem
Conventional vertical field-effect transistors (FETs) face challenges in scaling beyond the 7 nm node due to high aspect ratios, material thickness not scaling well, and high contact to gate capacitance, which limits the reduction of gate pitch.
Innovation Solution
The solution involves forming source and drain contacts at the ends of the vertical FETs instead of between them, reducing contact resistance and capacitance, and eliminating the shared contact between metal gate structures to create an air gap, allowing for a significant decrease in pitch between adjacent FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shared contacts are formed between gate material of adjacent vertical FETs, then contact resistance is reduced, but gate pitch cannot be scaled down due to material thickness constraints and leakage concerns
Solution Approach 1:
The patent extracts the shared contact structure from between the gate materials of adjacent vertical FETs and relocates it to the ends of the FETs. This removal of the intermediate shared contact eliminates the material thickness constraints and leakage paths that prevented pitch scaling, while maintaining low contact resistance through alternative contact configurations at the device ends.
Solution Approach 2:
The patent transitions the contact configuration from a planar shared contact between gates to a three-dimensional arrangement where contacts are positioned at the vertical ends of the FETs. This dimensional repositioning allows for air gaps or dielectric material between adjacent gate structures, enabling pitch reduction while maintaining electrical connectivity through the relocated contacts.
2Object-generated harmful factors
If insulator material is used between gate material of adjacent vertical FETs, then leakage is reduced, but gate pitch scaling is prevented due to material thickness requirements
Solution Approach 1:
The patent removes the insulator material layer that was previously required between the gate materials of adjacent vertical FETs. By eliminating this intermediate insulator layer through the relocation of contacts to the device ends, the patent enables direct air gaps or minimal dielectric spacing between gates, thereby reducing pitch while maintaining leakage protection through alternative isolation mechanisms.
3Quantity of substance
If vertical FETs are designed with channel perpendicular to substrate surface, then packing density is increased, but aspect ratio becomes too high causing manufacturing challenges
Solution Approach 1:
The patent modifies the vertical FET structure by repositioning contacts to the ends of the devices and introducing air gaps or reduced dielectric layers between adjacent gates. This dimensional reconfiguration allows for shorter effective channel lengths and reduced aspect ratios while maintaining the vertical channel orientation and high packing density benefits, making the devices manufacturable at scaled dimensions.
Data Source
AI summary
Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.