Vertical FET Gate-Source Overlap Reduction via Dielectric Spacer
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Solution Overview
Problem
Vertical FET designs experience excessive capacitive coupling between the gate and source/drain regions due to excessive overlap, which slows down transistor switching speed.
Innovation Solution
A dielectric region is introduced between the gate and the source/drain regions, increasing the distance between them and reducing capacitive coupling by selecting the vertical height dimension of the dielectric region to bring the capacitive coupling within an acceptable range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the gate and source/drain regions are positioned close together to increase device density, then device density is improved, but capacitive coupling between gate and source/drain increases
Solution Approach 1:
A dielectric region is introduced as an intermediary material between the gate and source/drain regions. This dielectric layer acts as a mediator that reduces the direct capacitive coupling while allowing the gate and source/drain to remain in close proximity for high device density. The dielectric region with lower permittivity than the surrounding medium provides electrical isolation while maintaining spatial compactness.
Solution Approach 2:
The permittivity parameter of the material between gate and source/drain is changed by using a dielectric region with lower permittivity compared to the default semiconductor material. This parameter change reduces the capacitive coupling strength (C = εA/d) while maintaining the same geometric configuration, thereby reducing harmful capacitance without sacrificing device density.
2Object-affected harmful factors
If the overlap between gate and source/drain is reduced to decrease capacitance, then capacitive coupling is reduced, but device density decreases
Solution Approach 1:
The dielectric region serves as a mediator that enables close spacing between gate and source/drain regions without direct capacitive coupling. This intermediary structure allows the transistor footprint to be minimized for high device density while the dielectric material prevents excessive capacitance formation, resolving the trade-off between density and capacitance reduction.
3Object-affected harmful factors
If the distance between gate and source/drain is increased to reduce capacitance, then capacitive coupling is reduced, but switching speed decreases
Solution Approach 1:
The permittivity parameter is changed by introducing a dielectric material with lower ε between gate and source/drain. This reduces capacitance (C proportional to ε) without changing the physical distance, thereby maintaining fast switching speed while reducing harmful capacitive coupling. The material parameter change achieves capacitance reduction without the geometric change that would slow switching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces unwanted capacitance, enhancing the switching speed of vertical FETs by minimizing the impact of gate/source/drain overlap.
Implementation Method 1
excessive capacitive coupling between the gate and source/drain regions
Implementation Method 2
forming a dielectric region over an upper surface of the source or the drain region
Data Source
AI summary
Embodiments of the invention are directed to a vertical FET device having gate and source or drain features. The device includes a fin formed in a substrate and a source or a drain region formed in the substrate. The device further includes a trench formed in the source or the drain region and a dielectric region formed in the trench. The device further includes a gate formed along vertical sidewalls of the fin and positioned such that a space between the gate and the source or the drain region includes at least a portion of the dielectric region. In some embodiments, the device further includes a bottom spacer formed over an upper surface of the dielectric region and positioned such that the space between the gate and the source or the drain region further includes at least a portion of the bottom spacer.