Vertical FET Gate Spacer Design for Electric Field Management
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Solution Overview
Problem
Vertical FETs face reliability issues due to high electric fields between the gate and source/drain regions, which can compromise device performance and reliability.
Innovation Solution
A semiconductor structure is formed with a liner removed from sidewalls, exposing the source/drain region, and a spacer layer is deposited on the dielectric material and source/drain region, followed by the formation of a gate material on the spacer layer, minimizing the distance between the gate and source/drain regions and reducing high electric fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional vertical FET structure is used, then the device footprint is reduced, but high electric fields develop between the gate and source/drain regions compromising reliability
Solution Approach 1:
A dielectric liner is introduced as an intermediary layer between the source/drain region and the gate. This liner acts as a mediator that reduces the direct electric field interaction between these regions, thereby lowering harmful high electric fields while maintaining the vertical FET's compact footprint and performance characteristics.
Solution Approach 2:
The electrical parameters of the interface between gate and source/drain are modified by introducing the dielectric liner. This changes the electric field distribution and reduces peak field strengths, improving reliability without sacrificing the device's vertical architecture benefits.
2Reliability
If the gate is positioned closer to the source/drain region, then device performance is improved, but electric field intensity increases reducing reliability
Solution Approach 1:
The dielectric liner serves as a physical and electrical intermediary that allows the gate to be positioned close to the source/drain region for performance while simultaneously reducing the harmful electric field effects, effectively decoupling the trade-off between proximity and reliability.
Data Source
AI summary
Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes forming a semiconductor fin on a source/drain region, forming a liner including a first dielectric material along sidewalls of the semiconductor fin and along sidewalls of the source/drain region, forming a second dielectric material along sidewalls of the liner including the first dielectric material, and removing the liner including the first dielectric material from sidewalls of the semiconductor fin. Removing the liner including the first dielectric material includes exposing portions of the source/drain region. The method further includes forming a spacer layer on the second dielectric material and portions of the source/drain region exposed by removing the liner including the first dielectric material and forming a gate material on the spacer layer.