Vertical FET Gate Contact Stacking to Shrink Fin Footprint
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Solution Overview
Problem
Conventional vertical field effect transistors (VTFETs) have a gap between the gate contact and the fin, leading to wasted space and increased size due to the lateral formation of the gate contact.
Innovation Solution
The gate contact is formed above the fin in the semiconductor stack, aligned vertically with the fin, using a doped fin and dielectric layers to separate it from the fin, eliminating the need for a gap and reducing the device's length or width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate contact is formed laterally away from the fin with a gap, then short circuits are avoided, but the device size increases and space is wasted
Solution Approach 1:
The gate contact is repositioned from a lateral arrangement to a vertical arrangement, stacking it above the fin structure. This dimensional change allows the gate contact to be directly over the fin without requiring a lateral gap, thus reducing device footprint while maintaining electrical isolation through the vertical fin-dielectric-gate contact stack.
Solution Approach 2:
The gate contact is nested vertically above the fin structure, with the dielectric layer positioned between them. This nesting arrangement allows compact vertical stacking of components, eliminating the need for lateral separation and reducing the overall device area while preventing short circuits through the intermediate dielectric layer.
2Reliability
If the gate contact is formed laterally away from the fin, then electrical isolation is maintained, but the length or width of the VTFET increases
Solution Approach 1:
The gate contact transitions from a lateral position to a vertical position above the fin. This repositioning in the vertical dimension eliminates the need for lateral extension, thereby reducing device length or width while maintaining electrical isolation through the vertical dielectric barrier between the fin and gate contact.
Solution Approach 2:
A dielectric layer is introduced as an intermediary between the fin and the gate contact in the vertical stack. This dielectric mediator provides electrical isolation, preventing short circuits while allowing the gate contact to be positioned directly above the fin, thus minimizing device footprint.
3Reliability
If a gap is left between the gate contact and the fin, then short circuits are prevented, but unused space increases
Solution Approach 1:
The isolation mechanism transitions from lateral gap spacing to vertical stacking with the gate contact positioned above the fin. This dimensional reorganization eliminates unused lateral space while maintaining short circuit prevention through the vertical dielectric layer positioned between the fin and gate contact.
Solution Approach 2:
The gate contact, dielectric layer, and fin are nested vertically in a compact stack, with the dielectric providing isolation. This nesting configuration eliminates wasted lateral space while preventing short circuits, as the dielectric layer acts as the isolation barrier in the vertical arrangement.
Data Source
AI summary
An apparatus includes a fin, a gate, and a gate contact. A portion of the fin is disposed in a first layer. The gate is disposed in the first layer and adjacent to the fin. The gate contact is disposed on the gate and in a second layer, wherein the second layer is disposed on the first layer such that the gate contact is above the fin.