Vertical FET Gate Trench Layout for Low On-Resistance Reliability
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Solution Overview
Problem
Vertical field-effect transistors with gate trenches face a trade-off between reducing on resistance and maintaining breakdown voltage, while also improving reliability by minimizing electric field strength at the tips of the gate trenches.
Innovation Solution
A chip-size-package type semiconductor device with a dual configuration, featuring a mix of shallow and deep gate trenches, where the number of deep trenches is at least 2 and at most n+1, with the same electric potential as the shallow trenches, to reduce on resistance and enhance tolerance to electric field strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the depth of gate trenches is increased to reduce on resistance, then on resistance decreases, but electric field strength at the tips of gate trenches increases causing reliability degradation
Solution Approach 1:
The patent applies local quality by creating two distinct types of gate trenches with different depths within the same device structure. First gate trenches have a first depth while second gate trenches have a second depth greater than the first depth. This local differentiation allows shallow trenches to control electric field strength at their tips for reliability, while deep trenches provide lower on resistance by extending further into the drift region.
Solution Approach 2:
The gate trench system is segmented into two functional groups: first gate trenches with smaller depth and second gate trenches with greater depth. The number of second gate trenches is controlled to be at least 2 and at most n+1 where n is the number of first gate trenches. This segmentation divides the single function of gate trenches into two complementary functions: electric field management and resistance reduction.
2Loss of energy
If the number of deep gate trenches is increased to further reduce on resistance, then on resistance decreases, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by precisely controlling the number of second gate trenches within a specific range (at least 2 and at most n+1 where n is the number of first gate trenches). This quantitative parameter control optimizes the balance between on resistance reduction and device complexity, avoiding excessive numbers of deep trenches while achieving the desired electrical characteristics.
Data Source
AI summary
A semiconductor device includes a vertical field-effect transistor including: a first gate trench and a second gate trench extending in a first direction, the second gate trench being deeper than the first trench; a first gate insulating film and a first gate conductor inside the first gate trench; and a second gate insulating film and a second gate conductor inside the second gate trench. The first gate conductor and the second gate conductor have the same potential. When a total number of first gate trenches is denoted by n, a total number of second gate trenches is at least 2 and at most n+1. In a second direction orthogonal to the first direction, the second gate trench is disposed at each of farthest ends of a region in which the first gate trenches and the second gate trenches are disposed.