Vertical FET Self-Aligned Contacts Low-k Spacers
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Solution Overview
Problem
Existing vertical transistors face challenges in maintaining yield and preventing shorting between contacts, which affects device scalability and performance due to the need for close spacing of contacts to avoid parasitic resistance and capacitance.
Innovation Solution
The design incorporates a fin structure with self-aligned isolation regions and low-k sidewall spacers composed of SiBCN or SiOCN, which facilitate contact alignment without shorting, reducing parasitic capacitance and allowing for more relaxed contact placement, thereby improving device density and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If contact spacing is reduced to improve device density, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs self-aligned processes where the isolation regions are formed automatically in precise positions relative to the gate structure and contacts without requiring additional alignment steps. The self-aligned contact formation process uses the gate structure and isolation regions as alignment references, allowing contacts to be precisely positioned at reduced spacing while maintaining manufacturing feasibility and high device density.
2Ease of manufacture
If self-aligned structures are used to improve contact alignment, then ease of manufacture is improved, but device complexity increases
Solution Approach 1:
The patent divides the device structure into distinct functional segments: gate structures, self-aligned isolation regions, and contacts. Each segment is formed through dedicated process steps that simplify the overall manufacturing. The isolation regions are segmented and positioned between specific contacts, creating a modular structure that improves ease of manufacture while managing device complexity through systematic organization of components.
Data Source
AI summary
A method of forming a semiconductor device is provided that includes forming a first source/drain region in a supporting substrate abutting a fin structure; and forming an isolation region in the supporting substrate adjacent to a first side of the fin structure, wherein the first source/drain region is positioned on an opposing second side of the fin structure. A gate structure is formed on the channel region portion of the fin structure. In a following step, a second source/drain region on an upper surface of the fin structure. Contacts can be formed aligned to the first source/drain region and the gate structure.