Vertical III-V FET Etch Depth Control Using a Marker Layer
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Solution Overview
Problem
The existing power transistor devices, particularly those with high-voltage handling capability, face challenges with slow switching speeds and high specific on-resistance, necessitating improved manufacturing control to enhance electrical performance.
Innovation Solution
The development of novel vertical-fin-based field-effect transistor (FET) and metal-oxide-semiconductor field-effect transistor (MOSFET) devices, involving a method of manufacturing that includes epitaxial growth of semiconductor layers, formation of marker layers, and precise etching to create fins and recess regions, thereby improving specific on-resistance, leakage current, and breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing processes are used for high-voltage power transistor devices, then breakdown voltage capability is achieved, but specific on-resistance increases and switching speeds decrease
Solution Approach 1:
The patent segments the semiconductor structure into multiple epitaxial layers with different dopant concentrations (first through fourth semiconductor layers) and introduces a marker layer for precise depth control. This segmentation allows optimization of each layer's electrical properties to simultaneously achieve high breakdown voltage and low on-resistance, resolving the contradiction between reliability and productivity.
Solution Approach 2:
The patent employs parameter changes by varying dopant concentrations across different epitaxial layers and using a marker layer with specific etch characteristics. The graded dopant concentrations in the second and third semiconductor layers enable precise control of electrical fields, allowing the device to achieve both high breakdown voltage and low specific on-resistance without compromising switching speed.
2Ease of manufacture
If etch depth control is not precisely managed, then manufacturing simplicity is maintained, but etch depth variations increase affecting device performance
Solution Approach 1:
The marker layer serves as an intermediary element during the etching process. It has distinct etch characteristics that allow it to be detected as the etch front approaches the target depth. This intermediary layer enables precise etch depth control without complicating the overall manufacturing process, as the marker layer can be removed or integrated into the final device structure.
Solution Approach 2:
The patent implements feedback control during etching by detecting the etching of the marker layer. When the marker layer is detected being etched, the process provides feedback to control the etch depth, ensuring precise termination. This feedback mechanism maintains manufacturing precision while keeping the process relatively simple through real-time monitoring.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in FET and MOSFET devices with improved electrical performance, including reduced specific on-resistance, lower leakage current, and enhanced breakdown voltage, while also providing better control over etch depth variations.
Implementation Method 1
etching at least a portion of the marker layer; detecting the etching of the at least a portion of the marker layer
Implementation Method 2
epitaxially growing a semiconductor layer in recess regions disposed between adjacent fins of the plurality of fins
Data Source
AI summary
A method of manufacturing a vertical FET device includes providing a semiconductor substrate structure including a marker layer; forming a hardmask layer coupled to the semiconductor substrate structure, wherein the hardmask layer comprises a set of openings operable to expose an upper surface portion of the semiconductor substrate structure; etching the upper surface portion of the semiconductor substrate structure to form a plurality of fins; etching at least a portion of the marker layer; detecting the etching of the at least a portion of the marker layer; epitaxially growing a semiconductor layer in recess regions disposed between adjacent fins of the plurality of fins; forming a source metal layer on each of the plurality of fins; and forming a gate metal layer coupled to the semiconductor layer.