Vertical FET Memory Access Devices for High-Density Arrays
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Solution Overview
Problem
Traditional non-volatile memory devices are large and consume high power, making them unsuitable for portable electronics, and as they shrink, they require improved memory access devices to handle high current densities without excessive 'off' state leakage.
Innovation Solution
The use of non-planar vertical FETs as memory access devices, which are formed in a vertical orientation with shared metal silicide contacts to reduce series resistance and parasitic resistance, and diode devices to prevent sneak current paths, allowing for high current delivery with low leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is decreased to increase density, then memory density is improved, but current density increases to extremely high levels requiring specialized access devices
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to vertical 3D architecture. Memory cells are stacked vertically with select devices positioned at different heights, allowing current to flow through vertical channels. This dimensional change enables higher density without proportionally increasing current density in any single plane, as the current path is distributed through multiple vertical layers.
Solution Approach 2:
The memory array is segmented into multiple blocks, each with its own select devices. Current paths are divided and routed through different select devices for different memory blocks, preventing excessive current concentration. The vertical stacking further segments the current path into discrete layers that can be independently controlled.
2Power
If high current is delivered to resistive memory cells for programming, then programming capability is achieved, but off-state leakage current increases
Solution Approach 1:
The select devices are designed with dynamic control capabilities, allowing their resistance state to be actively adjusted based on operational requirements. During programming operations, select devices are dynamically switched to low-resistance states to enable high current flow. During read or idle states, they transition to high-resistance states to minimize leakage, providing adaptive resistance control that optimizes both programming capability and leakage reduction.
Solution Approach 2:
Select devices function as intermediary elements between the word lines and memory cell arrays. These intermediary devices control and regulate current flow to the memory cells, enabling high current when needed for programming while blocking current during idle states. The select devices act as controlled gates that mediate between the input signals and the memory cells, preventing direct leakage paths.
3Ease of manufacture
If planar memory access devices are used, then device fabrication is simpler, but device area increases reducing memory density
Solution Approach 1:
The patent employs vertical FinFET structures instead of planar transistors. The FinFETs extend vertically from the substrate with gate electrodes wrapping around the fins, creating a three-dimensional active region. This vertical architecture dramatically reduces the footprint of each access device in the planar direction while maintaining or enhancing control capability, enabling higher memory density without sacrificing manufacturability through established FinFET fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables compact, high-current memory access with reduced power consumption and leakage, suitable for dense memory arrays and portable electronics.
Implementation Method 1
changing the cell resistance is accomplished by passing an electrical current of sufficient strength through the resistive memory cell
Implementation Method 2
shared metal silicide contacts to reduce series resistance and parasitic resistance
Implementation Method 3
diode devices to prevent sneak current paths, allowing for high current delivery with low leakage
Data Source
AI summary
A memory array that includes access devices that are each electrically coupled to more than one memory cell. The memory cells are coupled to the access devices via diode devices. The access devices include vertical semiconductor material mesas upstanding from a semiconductor base that form a conductive channel between first and second doped regions, and also planar access devices.