Vertical FET Memory Access Device for Cross-Point Arrays
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Solution Overview
Problem
Traditional non-volatile memory devices are large and consume high power, making them unsuitable for portable electronics, and as they shrink, they require improved memory access devices to handle high current densities without excessive 'off' state leakage.
Innovation Solution
The use of non-planar vertical FETs with metal silicide contacts to reduce parasitic resistance and enable high current flow through vertically oriented memory access devices, allowing for efficient programming and reset currents in resistive memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase density, then storage capacity is improved, but current density increases excessively leading to high power consumption and leakage
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to a vertically-oriented 3D structure. The vertically-oriented FET extends in the vertical dimension with source and drain regions at different heights, allowing current flow through the vertical channel. This dimensional change enables higher current density handling capability while maintaining smaller footprint area, thus improving storage capacity without proportionally increasing power consumption.
2Ease of manufacture
If planar access devices are used, then manufacturing is simpler, but device footprint is large and current handling capability is limited
Solution Approach 1:
The access device is reconfigured from a planar 2D structure to a vertically-oriented 3D structure. The vertically-oriented FET utilizes the vertical dimension for current flow, with the channel extending upward from the substrate. This reduces the lateral footprint area significantly while maintaining manufacturing compatibility with standard semiconductor processes through vertical epitaxial growth and doping techniques.
Solution Approach 2:
The patent employs composite material structures including vertically-oriented semiconductor layers with different doping types (n-type and p-type regions), metal silicide contacts for low-resistance connections, and insulating layers. This composite structure enables high current handling capability in a compact footprint while maintaining ease of manufacture through established semiconductor fabrication processes.
3Reliability
If high programming currents are applied to change resistance states, then memory programming is achieved, but off-state leakage current increases
Solution Approach 1:
The vertically-oriented FET structure confines the high programming currents to the vertical channel path between source and drain regions. The vertical geometry provides better current confinement and control compared to planar structures, reducing lateral leakage paths. The selectively doped vertical channel maintains low off-state leakage while enabling sufficient programming current when activated.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces size and power consumption while maintaining high current delivery, making non-volatile memory devices more suitable for portable electronics and improving memory access efficiency.
Implementation Method 1
non-planar vertical FETs with metal silicide contacts to reduce parasitic resistance and enable high current flow
Implementation Method 2
allowing for efficient programming and reset currents in resistive memory cells
Data Source
AI summary
A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to a second silicide layer on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.