Vertical FET Interconnect Layout With Multi-Height Metal Contacts
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Solution Overview
Problem
Existing processes face difficulties in forming double height or multi-height vertical metal structures for interconnection in semiconductor devices, which hinders the reduction of cell area and flexibility in semiconductor structure layouts.
Innovation Solution
The proposed semiconductor structure includes a conductive region disposed between upper and lower source/drain contacts, with metal gates electrically connected to the conductive region, allowing for varying lateral widths of source/drain contacts and reducing the cell area without compromising functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional planar metal structures are used for interconnection, then manufacturing process is simpler, but cell area cannot be reduced and layout flexibility is limited
Solution Approach 1:
The patent transitions from conventional planar (2D) metal interconnection structures to vertical (3D) metal structures that extend in the height dimension. Multiple metal layers are stacked vertically at different elevations, enabling interconnection in the vertical direction. This dimensional change reduces the lateral footprint and cell area while providing additional interconnection pathways, directly resolving the contradiction between area reduction and manufacturing complexity.
Solution Approach 2:
The patent divides the metal interconnection structure into multiple discrete layers at different elevations (first elevation, second elevation, third elevation). Each metal layer can be independently formed and controlled, allowing flexible routing and connection schemes. This segmentation enables the vertical stacking approach while maintaining manufacturability through standardized layer-by-layer fabrication processes.
2Area of stationary object
If vertical metal structures are formed to reduce cell area, then area is reduced, but process complexity increases
Solution Approach 1:
The patent employs a conductive region that serves multiple functions: it provides electrical connection between metal layers at different elevations, acts as an interconnection pathway, and can be integrated with the semiconductor device structure. This multi-functional design reduces the need for separate components and simplifies the overall manufacturing process despite the vertical complexity.
Solution Approach 2:
The patent introduces a conductive region as an intermediary element that facilitates connection between upper and lower source/drain contacts and metal gates. This intermediary structure simplifies the formation of vertical interconnections by providing a standardized interface between different elevation levels, reducing process complexity.
3Adaptability or versatility
If varying lateral widths of source/drain contacts are implemented, then layout flexibility is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements varying lateral widths for different source/drain contacts (first, second, third, and fourth source/drain contacts have different lateral widths). This dynamic geometric configuration allows flexible adaptation to different circuit layout requirements while maintaining functionality. The manufacturing process accommodates these variations through precise patterning techniques.
Data Source
AI summary
A semiconductor structure includes a first upper source/drain region, a second upper source/drain region, a first lower source/drain contact, a second lower source/drain contact, and a third conductive region. The first upper source/drain contact is disposed at a first elevation. The second upper source/drain contact is disposed at the first elevation. The first lower source/drain contact is disposed at a second elevation. The second lower source/drain contact is disposed at the second elevation. The third conductive region is disposed at a third elevation. A projection area of the third conductive region is disposed between a projection area of the first upper source/drain contact and a projection area of the second upper source/drain contact. The third elevation is disposed between the first elevation and the second elevation.