Vertical FET Multiplexer Reduces Footprint via Extraction
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Solution Overview
Problem
Conventional multiplexor integrated circuits require complex layouts and additional dummy devices for isolation, resulting in larger footprints and more complex interconnections due to the need for cross couple layers and diffusion breaks, which complicates the fabrication process and increases device size.
Innovation Solution
The use of vertical field effect transistors (VFETs) with unique geometric characteristics allows for a simplified design that eliminates the need for dummy devices and cross couple interconnections, enabling a reduced footprint and unidirectional interconnections, thereby forming a multiplexor with only four contact poly pitch (CPP) and improved device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar MOSFETs are used in multiplexor design, then the device can be fabricated using standard processes, but the footprint increases and requires dummy devices for isolation
Solution Approach 1:
The patent transitions from planar (2D) MOSFET architecture to vertical (3D) MOSFET architecture, changing the dimensionality of the device structure. This vertical configuration allows current to flow vertically through the channel rather than laterally, enabling compact integration and eliminating the need for dummy devices while maintaining standard fabrication compatibility
Solution Approach 2:
The invention extracts and eliminates the dummy devices that are traditionally required in planar MOSFET-based multiplexors for isolation purposes. The vertical FET structure inherently provides the necessary isolation and functionality without requiring these additional dummy components, thereby reducing the overall device footprint
2Reliability
If dummy devices and cross couple layers are used for isolation, then device isolation is achieved, but the layout complexity and interconnection complexity increase
Solution Approach 1:
The patent removes dummy devices and cross couple layers from the multiplexor design by utilizing the inherent isolation properties of the vertical FET structure. This extraction of unnecessary components directly reduces layout complexity and interconnection complexity while maintaining proper device isolation
Solution Approach 2:
The vertical FET structure provides self-isolation through its geometry and doping profiles, eliminating the need for external isolation structures like dummy devices. The device structure itself serves the isolation function, reducing overall design complexity
3Ease of manufacture
If conventional planar MOSFET layout is used, then standard fabrication processes can be applied, but cross couple interconnections are required increasing device size
Solution Approach 1:
The vertical FET architecture changes the interconnection topology by allowing gates to be connected vertically rather than requiring long lateral cross couple interconnections. This dimensional change reduces interconnection length while maintaining compatibility with standard fabrication processes
Data Source
AI summary
A method for forming a multiplexor integrated circuit includes employing four complementary pairs of vertical field effect transistor (VFET) pairs, each of the complementary pairs of VFETs includes a first VFET device having a gate and a second VFET device having a gate, the gate of the first VFET device is connected to the gate of the second VFET device. The four complementary pairs VFET pairs are arranged to form a signal input portion of the multiplexor with four contact poly pitch (CPP) The plurality source/drain connections are operably connected.