Vertical FET Contact Offset for Single-Direction IC Routing
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Solution Overview
Problem
The increasing density of integrated circuits (ICs) poses challenges in design and fabrication due to the complexity of routing conductive traces and the need for precise pitch alignment, which can lead to manufacturing errors and reduced packing efficiency.
Innovation Solution
A vertical stack of field-effect transistors (FETs) with fully independent source and drain contacts and a common gate, where the source and drain contacts of upper FETs are offset along the gate direction, allowing for increased routing flexibility and relaxed pitch requirements, enabling more efficient packing of conductive traces in a single direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conductive traces are routed in multiple directions to connect source and drain contacts, then routing flexibility is improved, but manufacturing precision deteriorates due to increased pitch alignment complexity
Solution Approach 1:
The source and drain contacts of upper FETs are offset asymmetrically relative to lower FETs, creating an interdigitated pattern that enables single-direction routing while maintaining access to all contacts. This asymmetric arrangement eliminates the need for multi-directional trace routing, thereby preserving manufacturing precision.
Solution Approach 2:
The patent utilizes vertical stacking of FETs in the third dimension to achieve routing flexibility that would otherwise require complex two-dimensional trace patterns. By stacking FETs vertically and offsetting contacts in the lateral direction, the design enables all connections to be made in a single routing direction without compromising adaptability.
2Productivity
If IC density is increased to improve functionality and reduce cost, then productivity is improved, but device complexity increases leading to design and fabrication difficulties
Solution Approach 1:
The patent transitions from planar to vertical device architecture by stacking multiple FETs in the vertical dimension. This enables higher IC density and functionality without proportionally increasing lateral footprint or routing complexity, as all connections can be made in a single direction through the offset contact arrangement.
Solution Approach 2:
The vertical stack divides the device into discrete FET segments with independent source and drain contacts. Each FET in the stack can be independently accessed and routed, simplifying the overall design and fabrication process while enabling high-density integration of multiple functional units.
3Ease of manufacture
If pitch requirements are relaxed to simplify manufacturing, then ease of manufacture is improved, but packing density of conductive traces deteriorates
Solution Approach 1:
By utilizing vertical stacking, the patent achieves high packing density of conductive traces in the lateral dimension without requiring tight pitch control in multiple directions. The single-direction routing approach maintains trace packing efficiency while significantly simplifying manufacturing pitch requirements.
Data Source
AI summary
An IC device includes a gate extending along a first axis, a first channel extending through the gate along a second perpendicular axis at a first elevation along a third axis perpendicular to the first and second axes, first and second source/drain (S/D) structures adjacent to opposite ends of the first channel at the first elevation, a second channel extending through the gate along the second axis at a second elevation along the third axis, and third and fourth S/D structures adjacent to opposite ends of the second channel at the second elevation. Each of one of the first or third and one of the second or fourth S/D structures extends along a first segment of the first axis, and each of the other of the first or third and second or fourth S/D structures extends along a second segment of the first axis different from the first segment.