Vertical FET Pair With Shared Source-Drain Region
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Solution Overview
Problem
Conventional multi-gate non-planar field effect transistors (MUGFETs) face limitations in further size scaling due to requirements for minimum gate length, pitch between source/drain contacts, and semiconductor fin height, which restricts transistor width and drive current.
Innovation Solution
The semiconductor structure comprises a pair of vertical field effect transistors formed from an U-shaped semiconductor body with a shared source/drain region and multiple gates, allowing for vertical gate configuration and reduced contact pitch, enabling continued size scaling without the limitations of conventional MUGFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional MUGFETs use multiple semiconductor fins to increase transistor width, then drive current increases, but pitch between semiconductor fins must be sufficiently large to allow gate material deposition, limiting further size scaling
Solution Approach 1:
The patent transitions from planar fin structures to vertical channel structures where the channel extends vertically from the substrate. This dimensional change allows gate material to be deposited conformally on the vertical sidewalls, eliminating the need for large horizontal pitch between fins while maintaining effective gate control. The vertical orientation enables tighter packing of multiple fins in the horizontal plane, increasing transistor width and drive current without compromising manufacturability.
2Length of moving object
If MUGFETs reduce gate length to scale down device size, then device footprint decreases, but short channel effects increase and drive current decreases
Solution Approach 1:
The patent employs vertical channel structures that extend perpendicular to the substrate, transforming the traditional planar gate-channel interface into a three-dimensional configuration. This vertical geometry provides enhanced gate control over the channel through wraparound gates that contact the channel from multiple directions, effectively suppressing short channel effects even when horizontal gate length is reduced for scaling.
Solution Approach 2:
The patent implements wraparound gates that envelop the vertical channel structure, with gate material conformally coating the channel sidewalls. This nested configuration allows the gate to control the channel from multiple angles, providing superior electrostatic control and reducing short channel effects compared to planar gate structures.
3Area of stationary object
If MUGFETs reduce contact pitch to increase device density, then more transistors fit in given area, but minimum gate length requirements prevent further reduction
Solution Approach 1:
The patent utilizes vertical channel structures that decouple the gate length dimension from the contact pitch dimension. Since the channel extends vertically rather than horizontally, the horizontal pitch between contacts can be reduced independently of gate length constraints, enabling higher device density without compromising transistor performance.
Data Source
AI summary
Disclosed are semiconductor structures and methods of forming the structures. The structures each comprise a pair of vertical FETs. Specifically, a U-shaped semiconductor body has a horizontal section and two vertical sections. The horizontal section comprises a shared source/drain region for first and second vertical FETs. Each vertical section comprises a channel region and a source/drain region above the channel region for a corresponding one the vertical FETs. In one semiconductor structure, each vertical section has a gate wrapped around the channel region. In another semiconductor structure, each vertical section has a front gate positioned adjacent to the inner vertical surface at the channel region and a back gate positioned adjacent to the outer vertical surface at the channel region. In any case, a contact, which is electrically isolated from the gates, extends vertically to the shared source/drain region in the horizontal section. Optionally, metal strap(s) electrically connect the pair of vertical FETs to adjacent pair(s).