Vertical FET ReRAM Integration via Epitaxial Tip Field Enhancement
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Solution Overview
Problem
Current semiconductor technologies face challenges in integrating resistive memory elements effectively with vertical transistors, particularly in achieving efficient resistive switching and scalable memory solutions for high-density and low-power applications.
Innovation Solution
The integration of a resistive memory element with a vertical field effect transistor (FET) is achieved by forming an epitaxial tip that defines a drain terminal, allowing a current conducting filament to form at the epitaxial tip due to electric field enhancement, and connecting the vertical FET and oxide ReRAM in series to form a 1T1R configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If variable resistance memory elements are connected between two orthogonally extending conductors in a two-dimensional array, then memory state can be changed by proper voltages, but integration density and scalability are limited
Solution Approach 1:
The patent transitions from a two-dimensional array structure to a three-dimensional vertical structure by stacking the resistive memory element directly on top of the transistor. This vertical integration approach increases memory integration density by utilizing the third dimension (height) rather than only expanding in the planar direction, thereby solving the scalability limitation of traditional two-dimensional crosspoint architectures.
2Quantity of substance
If resistive memory elements are integrated with vertical transistors for high-density applications, then memory density increases, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the transistor fabrication process with the resistive memory element formation by integrating both structures within the same semiconductor device. The resistive memory element is formed directly on the transistor substrate, allowing shared processing steps and reducing the number of separate fabrication operations required, thereby managing manufacturing complexity while achieving high memory density.
Solution Approach 2:
The patent performs preliminary actions by forming the transistor structure first, then sequentially forming the resistive memory element on top. This staged approach allows each component to be optimized independently before integration, simplifying the overall manufacturing process by breaking down the complex integration task into manageable sequential steps rather than attempting simultaneous formation.
3Use of energy by moving object
If high-k based ReRAM is used for low-power applications, then power consumption decreases, but set voltage and reset current control becomes challenging
Solution Approach 1:
The patent utilizes parameter changes by employing high-k dielectric materials with different capacitance characteristics to control the electric field distribution in the resistive memory element. By adjusting the dielectric constant and thickness parameters of the high-k layer, the set voltage and reset current can be precisely controlled, enabling low-power operation while maintaining accurate voltage control through material parameter optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach lowers the set voltage and reset current of high-k based ReRAM, enabling high-density, fast, and low-power memory solutions suitable for neuromorphic computing and non-volatile memory applications, with enhanced electric field aiding in filament formation and memory cell integration on the drain side of a vertical transistor.
Implementation Method 1
allowing a current conducting filament to form at the epitaxial tip due to electric field enhancement
Data Source
AI summary
A method is presented for integrating a resistive random access memory (ReRAM) device with vertical transistors on a single chip. The method includes forming a vertical field effect transistor (FET) including an epitaxial tip defining a drain terminal and forming the ReRAM device in direct contact with the epitaxial tip of the vertical FET such that a current conducting filament is formed at the epitaxial tip due to electric field enhancement.