Vertical FET Resistance Control Using Energy Barrier Channel Structure
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Solution Overview
Problem
Conventional semiconductor devices, such as field effect transistors (FETs), face challenges in achieving controllable resistance levels above a predetermined threshold, particularly in vertical FETs, which results in high parasitic capacitance and reduced performance due to the vertically stacked configuration and reduced footprint, leading to issues like RC delay and power dissipation.
Innovation Solution
The development of semiconductor devices with a crosspoint array structure using resistive processing units (RPUs) that incorporate FETs with a controllable resistance above 10 MΩ, achieved through the formation of energy barriers and gate stacks, allowing for local data storage and processing within the RPU array, enabling parallel matrix multiplication and efficient neural network training.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If FETs are used in vertical configuration with stacked structure, then device footprint is reduced, but parasitic capacitance increases
Solution Approach 1:
The patent segments the channel into multiple independent vertical segments (first channel segment, second channel segment, third channel segment) along the vertical axis. Each segment can be independently controlled by its own gate, allowing the device to achieve low parasitic capacitance through segmented architecture while maintaining compact footprint.
Solution Approach 2:
The patent transitions from conventional lateral FET configuration to vertical FET configuration, utilizing the vertical dimension for channel extension. This dimensional change enables reduced footprint while managing parasitic capacitance through the segmented vertical architecture with intermediate source/drain regions.
2Productivity
If FET resistance is increased above 10 MΩ for neural network applications, then training efficiency improves, but control precision becomes difficult to achieve
Solution Approach 1:
The patent implements dynamic resistance control through multiple independently controlled channel segments. Each segment can be adjusted via its gate to achieve desired resistance values, enabling precise control of overall device resistance above 10 MΩ while maintaining training efficiency for neural network applications.
Solution Approach 2:
The patent achieves precise resistance control by changing multiple parameters including channel segment dimensions, doping concentrations, gate voltages, and material compositions. These parameter adjustments enable resistance values above 10 MΩ with controlled precision for neural network training operations.
3Productivity
If conventional FETs are used in crossbar arrays, then circuit density is achieved, but RC delay and power dissipation increase
Solution Approach 1:
The segmented vertical channel architecture reduces RC delay by dividing the channel into smaller segments with intermediate source/drain regions. This segmentation reduces the overall resistance and capacitance product while maintaining high circuit density in crossbar array configurations.
Solution Approach 2:
The vertical FET configuration with segmented channels enables high circuit density in crossbar arrays while reducing RC delay through the three-dimensional architecture. The vertical orientation and segmented structure reduce parasitic effects compared to conventional lateral configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the performance of artificial neural networks by enabling high resistive, controllable FETs for use in RPU arrays, improving training speed and efficiency while reducing power consumption, thereby addressing the limitations of existing FETs in neural network applications.
Implementation Method 1
An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier
Implementation Method 2
a conductive gate stack is formed over the channel region
Data Source
AI summary
A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.