Vertical FET Structure With Schottky Reverse Conduction

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Solution Overview

Problem

Conventional GaN-based VHEMT transistors suffer from high conduction losses in reverse operation due to the high forward voltage of the p-n junction, leading to inefficient energy use and increased electrical losses.

Innovation Solution

Integrate a Schottky or hetero-diode within the vertical field-effect transistor to replace the p-n diode, reducing conduction losses and maintaining a normally-off operation with low sheet resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a p-n junction body diode is used for reverse operation, then the transistor can operate in reverse mode, but high conduction losses occur due to high forward voltage of approximately 3 V

Engineering Contradiction:
Improvereverse operation capabilityVSAvoidconduction losses
Core Design Contradiction:
Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The patent changes the fundamental parameter of the diode structure from a p-n junction to a Schottky contact. This parameter change reduces the forward voltage from approximately 3 V to a significantly lower value, thereby reducing conduction losses in reverse operation while maintaining the ability to operate in reverse mode

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces an additional Schottky contact that creates a parallel conduction path for reverse operation. This copied diode function with different physical characteristics (Schottky instead of p-n junction) provides low-loss reverse conduction alongside the original transistor functionality

Inventive Principle:
Principle #26Copying

2Loss of energy

If a Schottky contact is added for low-loss reverse operation, then conduction losses are reduced, but the device structure becomes more complex

Engineering Contradiction:
Improveconduction lossesVSAvoidstructure complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent merges the Schottky contact with the existing transistor structure by forming it on the drift region, which is already present in the VHEMT architecture. This integration approach adds the low-loss reverse conduction capability while minimizing structural complexity increases, as the Schottky contact shares the same physical space and fabrication processes as the existing device

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The integration of a Schottky or hetero-diode significantly reduces forward voltages, enhancing the efficiency of the transistor by minimizing conduction losses and maintaining switching performance.

Implementation Method 1

a contact structure at least partially on or over the drift region, which forms a Schottky- or hetero-contact at least with the drift region

Methodology Applied
Scientific EffectSchottky barrier: Conduction (electrical)

Implementation Method 2

a groove structure having at least one side wall on which a field-effect transistor (FET)-channel region is formed, the FET-channel region having a III-V-heterostructure for forming a two-dimensional charge-carrier gas, e.g., an electron gas, at an interface of the III-V-heterostructure

Methodology Applied
Scientific EffectTwo-dimensional electron gas formation: Conduction (electrical)

Data Source

PatentUS12495570B2Vertical field-effect transistor, method for producing a vertical field-effect transistor and component having vertical field-effect transistors
Publication Date: 2025.12.09 ROBERT BOSCH GMBH
  • US12495570B2 patent drawing
  • US12495570B2 patent drawing
  • US12495570B2 patent drawing

AI summary

A vertical field-effect transistor. The vertical field-effect transistor has: A first semiconductor layer, which has a p-type conductivity, on or over a drift region; a groove structure which penetrates the first semiconductor layer vertically, the groove structure having at least one side wall on which a field-effect transistor (FET)-channel region is formed, the FET-channel region having a III-V-heterostructure for forming a two-dimensional electron gas at an interface of the III-V-heterostructure; a source-drain electrode which is electroconductively connected to the III-V-heterostructure; and a contact structure at least partially on or over the drift region, which forms a Schottky- or hetero-contact at least with the drift region, the contact structure being electroconductively connected to the source-drain electrode, and at least the region lying vertically between the contact structure and the drift region being free of the first semiconductor layer.