Vertical FET Structure with Segmented Gate and Source Drain
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Solution Overview
Problem
Vertical field effect transistors (FETs) face challenges in reducing parasitic resistance and achieving different gate lengths and better isolation in a single semiconductor structure.
Innovation Solution
A semiconductor structure comprising a substrate, conductor, and dielectric layers with a through hole filled with semiconductor material, where conductor plugs serve as source/drain and gate electrodes, and a method involving layer formation and etching to achieve vertical FETs with varied gate lengths and improved isolation through the Damascene Process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional vertical FET structure is used, then device integration is achieved, but parasitic resistance remains high
Solution Approach 1:
The source and drain regions are segmented into multiple sections along the vertical channel, with each section having its own contact structure. This segmentation allows current to flow through multiple parallel paths, reducing the overall parasitic resistance while maintaining the vertical FET architecture
Solution Approach 2:
The patent transitions from planar contact structures to three-dimensional vertical contact structures. Conductor plugs extend vertically through insulating layers to contact different segments of the source/drain regions, adding a vertical dimension to current flow paths and reducing resistance
2Ease of manufacture
If single gate length is used, then manufacturing is simplified, but device versatility is limited
Solution Approach 1:
The gate structure is divided into multiple segments with different lengths along the vertical channel. Each gate segment can be independently controlled, allowing the device to function as multiple FETs with different gate lengths within a single structure, achieving both manufacturing simplicity and device versatility
Solution Approach 2:
The vertical FET structure is designed to serve multiple functions simultaneously - it can operate as different types of transistors (e.g., NFET, PFET) with different gate lengths using the same basic architecture, making the structure universally applicable for various logic functions
3Productivity
If devices are placed close together, then integration density is improved, but isolation between devices becomes difficult
Solution Approach 1:
The patent uses vertical stacking of insulating layers and conductor plugs to achieve device isolation in the vertical dimension rather than relying solely on lateral separation. This allows closely spaced devices to be properly isolated while maintaining high integration density
Data Source
AI summary
The invention discloses a semiconductor structure comprising: a substrate, a conductor layer, and a dielectric layer surrounding the conductor layer on the substrate; a first insulating layer covering both of the conductor layer and the dielectric layer; a gate conductor layer formed on the first insulating layer, and a dielectric layer surrounding the gate conductor layer; and a second insulating layer covering both of the gate conductor layer and the dielectric layer surrounding the gate conductor layer; wherein a through hole filled with a semiconductor material penetrates through the gate conductor layer perpendicularly, the bottom of the through hole stops on the conductor layer, and a first conductor plug serving as a drain/source electrode is provided on the top of the through hole; and a second conductor plug serving as a source/drain electrode electrically contacts the conductor layer, and a third conductor plug serving as a gate electrode electrically contacts the gate conductor layer.