Vertical FET With Segmented Gate Electrodes
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Solution Overview
Problem
Vertical field effect transistors face performance degradation due to high leakage current and low on-current, primarily attributed to crystalline defects and limitations in the spatial extent of the depletion zone, which hinder their ability to provide high on-current and well-defined threshold voltage.
Innovation Solution
The semiconductor device design includes a vertical field effect transistor structure with inner and outer gate electrodes, dielectrics, and semiconductor channel strips, featuring a laterally-undulating gate dielectric layer and gate electrodes, along with bottom and top active regions, to enhance electrical performance and control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional vertical field effect transistor structure is used, then the device complexity is low, but the on-current is low and off-current is high due to crystalline defects and limited depletion zone
Solution Approach 1:
The gate structure is segmented into multiple independent gate electrodes (first gate electrode, second gate electrode, third gate electrode) positioned at different heights along the channel. Each gate can independently control the depletion zone at its respective location, allowing precise control of carrier flow and enabling high on-current while maintaining low off-current through coordinated gating.
Solution Approach 2:
The invention transitions from a conventional planar gate structure to a three-dimensional vertical architecture where gates are stacked at different heights along the channel length. This vertical stacking enables control of the depletion zone in the vertical dimension, expanding the effective control volume and improving electrical performance without increasing lateral footprint.
2Reliability
If the spatial extent of the depletion zone is limited, then the device structure remains simple, but the on-current cannot be sufficiently high
Solution Approach 1:
The depletion zone control is segmented into multiple zones, each controlled by a separate gate electrode positioned at different heights. The first gate electrode controls a first depletion zone, the second gate electrode controls a second depletion zone, and the third gate electrode controls a third depletion zone. This segmentation allows the total effective depletion zone extent to be the sum of individual zones, achieving high on-current through cumulative depletion control.
Solution Approach 2:
The depletion zone is extended into the vertical dimension through stacked gate electrodes at different heights. Instead of relying solely on lateral depletion zone extent, the invention creates a three-dimensional depletion control volume where gates at different vertical positions collectively manage carrier flow, effectively increasing the total depletion zone extent and enabling high on-current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the on-current and reduces off-current, achieving superior performance by effectively managing the depletion zone and electrical control within the transistors.
Implementation Method 1
a first gate dielectric layer and a first gate electrode forming a first gate, each extending along a first horizontal direction, the first gate electrode laterally confined by the first gate dielectric layer
Implementation Method 2
a pair of vertical semiconductor channel strips, each including a first sidewall contacting a respective one of the pair of inner gate dielectrics
Data Source
AI summary
A matrix rail structure is formed over a substrate. The matrix rail structure includes a pair of lengthwise sidewalls that extend along a first horizontal direction and comprises, or is at least partially subsequently replaced with, a set of at least one gate electrode rail extending along the first horizontal direction and straight-sidewalled gate dielectrics. A pair of vertical semiconductor channel strips and a pair of laterally-undulating gate dielectrics can be formed on sidewalls of the matrix rail structure for each vertical field effect transistor. At least one laterally-undulating gate electrode extending along the first horizontal direction is formed on the laterally-undulating gate dielectrics. Bottom active regions and top active regions are formed at end portions of the vertical semiconductor channel strips. The vertical field effect transistors can be formed as a two-dimensional array, and may be employed as access transistors for a three-dimensional memory device.