Vertical FET Two-Tier Select Gates for Leakage Suppression
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Solution Overview
Problem
Current semiconductor technologies face challenges in efficiently manufacturing three-dimensional memory devices with high-density, low-power operation, particularly in forming reliable two-dimensional arrays of vertical field effect transistors with effective select gates for resistive random access memory (ReRAM) applications.
Innovation Solution
A semiconductor structure comprising a two-dimensional array of vertical field effect transistors with a two-tier select gate configuration is developed, featuring a first-tier structure of alternating semiconductor rail and dielectric isolation rails, and a second-tier structure of composite rail and dielectric isolation rails, along with specific gate dielectrics and electrodes, to enhance selectivity and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single-tier select gate configuration is used, then the device structure is simpler, but the selectivity and leakage suppression are insufficient
Solution Approach 1:
The select gate is divided into two distinct tiers: a first select gate (SG1) formed on semiconductor rails and a second select gate (SG2) formed on composite rails. This segmentation allows each gate to independently control different aspects of current flow, thereby improving selectivity and leakage suppression without requiring excessive complexity in a single gate structure.
Solution Approach 2:
The patent transitions from a planar single-tier gate configuration to a three-dimensional two-tier vertical configuration. The first select gate operates at a lower vertical level while the second select gate operates at an upper vertical level, creating a stacked architecture that enhances control over current paths in the vertical dimension, thereby improving selectivity.
2Quantity of substance
If high-density memory structures are implemented, then storage capacity increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
The memory structure is segmented into distinct functional regions: semiconductor rails for current conduction, composite rails with alternating semiconductor and dielectric pillars for isolation and control, and two-tier select gates for selective activation. This segmentation allows each component to be optimized and manufactured independently, reducing the cumulative precision requirements compared to a monolithic high-density structure.
Solution Approach 2:
Dielectric isolation rails and dielectric pillar structures serve as intermediary elements between active semiconductor components. These intermediary structures provide physical and electrical isolation, enabling higher density packing of memory cells while maintaining manufacturing feasibility through standardized formation processes.
3Loss of energy
If low-power operation is achieved through leakage suppression, then energy efficiency improves, but device complexity increases due to additional select gates
Solution Approach 1:
The power loss reduction is achieved by segmenting the control function into two select gates: SG1 for row selection and SG2 for column selection. This segmentation enables precise control of current paths, suppressing leakage current at multiple stages without requiring a single complex high-power gate.
Solution Approach 2:
The two-tier vertical configuration of select gates creates additional control dimensions for suppressing leakage current. The first select gate controls current in the lower vertical region while the second select gate controls current in the upper vertical region, providing multi-level leakage suppression that improves energy efficiency.
Data Source
AI summary
A two-dimensional array of vertical field effect transistors is provided, which includes a first-tier structure and a second-tier structure. The first-tier structure includes a laterally alternating sequence of semiconductor rail structures and first dielectric isolation rails that alternates along a first horizontal direction. A first gate dielectric and a first gate electrode that laterally extend along a second horizontal direction are disposed between each neighboring pair of a semiconductor rail structure and a first dielectric isolation rail. The second-tier structure includes a laterally alternating sequence of composite rail structures and second dielectric isolation rails that alternates along the second horizontal direction. Each of the composite rail structures includes a laterally alternating plurality of semiconductor pillar structures and dielectric pillar structures. A second gate dielectric and a second gate electrode are disposed between each neighboring pair of a composite rail structure and a second dielectric isolation rail.