Vertical FET Self-Aligned Block for Dense Replacement Gate Layouts
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in increasing the density and efficiency of vertical field-effect transistors (FETs) per unit area, particularly in integrating self-aligned blocks between vertical pFETs and nFETs to enhance compute power.
Innovation Solution
The method involves forming channel fins with self-aligned blocks between pFET and nFET structures, using sacrificial gates and vertical liners to create a metallization contact trench, and replacing the sacrificial gates with replacement gates while maintaining a self-aligned block to increase density and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional fabrication methods are used without self-aligned blocks, then manufacturing process is simpler, but density and compute power of vertical FET structures are reduced
Solution Approach 1:
The fabrication process is divided into distinct stages: forming sacrificial gates on sidewalls, depositing vertical liners, creating self-aligned blocks between adjacent FETs, removing sacrificial gates, and forming replacement gates. This segmentation allows each step to be optimized independently while achieving high density through precise spatial control of components
Solution Approach 2:
Sacrificial gates are formed on the sidewalls of channel fins before the main gate structure is created. These preliminary structures serve as placeholders that define the eventual position of the self-aligned blocks and replacement gates, enabling precise alignment without requiring complex lithography steps later in the process
2Power
If self-aligned blocks are integrated between pFETs and nFETs, then compute power and efficiency are enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The self-aligned block structure utilizes the vertical liners and sacrificial gates as self-aligning features. When materials are deposited conformally on the sidewalls and subsequent etching is performed, the self-aligned block automatically positions itself relative to adjacent pFET and nFET structures without requiring additional alignment steps, thereby achieving high precision through self-organization rather than external control
3Productivity
If replacement gates are formed after removing sacrificial gates, then vertical FET structure efficiency is improved, but fabrication time increases
Solution Approach 1:
The removal of sacrificial gates and the formation of replacement gates are combined into a single integrated process sequence. The self-aligned blocks that remain after sacrificial gate removal immediately serve as alignment references for depositing the replacement gate material, eliminating the need for separate alignment and positioning steps. This merging of operations reduces the total fabrication cycle time while maintaining the efficiency benefits of the replacement gate structure
Data Source
AI summary
A vertical FET includes a channel fin between a bottom source/drain (S/D) region and a top S/D region, a gate upon a sidewall of the channel fin, a top metallization upon the top S/D region, a first contact metallization connected to the gate, a second contact metallization connected to the bottom S/D region, a first vertical liner between a portion of the gate and the first contact metallization, and a second vertical liner between the top metallization and the second contact metallization. The vertical FET may be fabricated by forming a self-aligned block and utilizing the self-aligned block to e.g., prevent gate to gate shorting during replacement gate formation or processing.