Self-Aligned Source/Drain Contact for Vertical FET
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Solution Overview
Problem
Current vertical field-effect transistor (VFET) designs have a large distance between source/drain contacts and fin tips due to concerns about gate and source/drain contact overlays, leading to increased device size and reduced fin length, which degrades performance and integration density.
Innovation Solution
A method is developed to form a self-aligned bottom source/drain contact by exposing a portion of the bottom source/drain region and forming a dielectric spacer on the fin, allowing the contact to be in close proximity to the vertical channel region, thereby reducing the distance between the source/drain contacts and fin ends.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between source/drain contacts and fin tips is increased to prevent overlay and short issues, then manufacturing reliability is improved, but device size increases and integration density decreases
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional vertical structure by forming fins that extend vertically from the substrate. This vertical dimension allows source/drain contacts to be positioned closely to fin tips without causing overlay or short issues, as the gate wraps around the fin structure providing control in multiple dimensions. The self-aligned formation of contacts at the fin ends in this vertical architecture prevents manufacturing defects while maintaining compact device footprint.
Solution Approach 2:
The patent introduces a dielectric spacer as an intermediary element positioned between the source/drain contact and the fin structure. This spacer provides physical separation and electrical isolation, preventing direct contact between the metal contact and the semiconductor fin, thereby eliminating short circuit risks while allowing the contact to be positioned in close proximity to the fin tip for low resistance connection.
2Reliability
If the distance between source/drain contacts and fin tips is increased, then manufacturing reliability is improved, but middle of line resistance increases
Solution Approach 1:
The vertical fin structure enables the source/drain contact to be positioned at the fin end in three-dimensional space, minimizing the current path length through the semiconductor material. The gate wrapping around the vertical fin provides effective channel control despite the reduced horizontal distance, preventing short-channel effects while reducing middle of line resistance through the optimized vertical current flow path.
Solution Approach 2:
The dielectric spacer serves as a mediator that provides electrical isolation without increasing the current path length. By positioning the spacer vertically alongside the fin rather than horizontally between contact and fin, the patent maintains a short current path through the source/drain region while still providing necessary electrical separation to prevent shorts and overlay issues.
3Reliability
If fin length is reduced to accommodate larger contact-to-fin distance, then manufacturing reliability is improved, but device performance degrades
Solution Approach 1:
The patent forms vertical fins extending upward from the substrate, creating a three-dimensional channel structure. This vertical orientation allows the effective channel length to be determined by the fin height rather than horizontal distance, enabling shorter horizontal layouts while maintaining adequate channel control. The gate wrapping around the vertical fin structure provides effective electrostatic control of the channel, preventing short-channel effects even with reduced device dimensions.
Solution Approach 2:
The dielectric spacer acts as a mediator that enables close positioning of source/drain contacts to vertical fin tips without causing manufacturing defects. This allows the fin length to be optimized for performance rather than being constrained by excessive contact-to-fin distances, maintaining high device performance while achieving reliable fabrication.
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a fin on a semiconductor substrate. In the method, a bottom source/drain region is formed between the fin and the semiconductor substrate, and a top source/drain region is formed on the fin. The method further includes forming a cap layer covering part of a top surface of the top source/drain region. A portion of the top source/drain region and an underlying portion of the fin not covered by the cap layer are removed. The removal exposes a portion of the bottom source/drain region. A dielectric spacer is formed on a side of the fin adjacent the exposed portion of the bottom source/drain region, and extends onto a side of the top source/drain region. A bottom source/drain contact is formed on the exposed portion of the bottom source/drain region and on the dielectric spacer.