Vertical FET Cell Height Reduction via Self-Aligned Gate and Source/Drain Contacts
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Solution Overview
Problem
Aggressive scaling of semiconductor devices leads to challenges such as parasitic capacitance and short circuits due to decreased spacing between conductive elements, necessitating methods for manufacturing advanced node VFET devices with reduced footprint without compromising performance and reliability.
Innovation Solution
A process is developed to form self-aligned bottom S/D contacts and self-aligned gate contacts, reducing the VFET cell height by controlling distances L1 and L2, which is achieved through specific fabrication steps including forming a bottom S/D layer, spacer layers, high-k metal gate layers, and interlayer dielectric layers, allowing for precise etching and contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional fabrication processes are used for VFET devices, then manufacturing simplicity is maintained, but device footprint and cell height cannot be sufficiently reduced
Solution Approach 1:
The methodology performs preliminary actions by forming spacer layers and performing timed etches before final contact formation. The gate spacer is formed on the high-k metal gate layer, and a timed etch is performed to expose the bottom S/D layer, enabling self-aligned contact formation that reduces footprint while managing complexity through structured process sequencing.
Solution Approach 2:
The fabrication process employs self-aligned formation where the gate spacer automatically defines the contact alignment. The timed etch process uses the gate spacer as a self-aligned mask, eliminating the need for separate alignment steps and reducing device footprint without proportionally increasing process complexity.
2Area of moving object
If spacing between conductive elements is decreased to reduce footprint, then device density increases, but parasitic capacitance and short circuits increase
Solution Approach 1:
The gate spacer serves as an intermediary element between the high-k metal gate layer and the bottom S/D contact. This spacer layer provides electrical isolation and prevents direct contact between conductive elements, thereby reducing parasitic capacitance and preventing short circuits while enabling reduced spacing for smaller footprint.
Solution Approach 2:
The fabrication process segments the conductive elements with insulating spacer layers. The gate spacer divides the structure into electrically isolated regions, preventing unwanted electrical interaction between the gate and S/D contacts, thus reducing parasitic effects while maintaining compact geometry.
3Area of moving object
If self-aligned contact formation is implemented to reduce cell height, then device density improves, but manufacturing precision requirements increase
Solution Approach 1:
The gate spacer acts as a self-aligned mask during the timed etch process, automatically defining the contact opening position without requiring separate alignment steps. This self-service mechanism reduces cell height through precise self-aligned contact formation while managing manufacturing precision requirements through the inherent alignment provided by the spacer structure.
Solution Approach 2:
The methodology replaces mechanical alignment systems with a chemically-driven self-aligned etch process. The timed etch uses the gate spacer as a chemical mask, substituting precise mechanical positioning with a self-aligned chemical process that achieves the required precision for reduced cell height.
Data Source
AI summary
A method of forming a semiconductor device includes: forming a bottom source or drain (S/D) layer on a substrate; forming a bottom spacer layer on the bottom S/D layer; forming a vertical transistor channel on the bottom S/D; forming a high-k metal gate layer on sides of the vertical transistor channel and above the bottom S/D layer; forming a gate spacer on sides of the vertical transistor channel and on top of the high-k metal gate layer; covering the high-k metal gate layer, the vertical transistor channel and bottom S/D layer with an interlayer dielectric (ILD); forming with a non-self-aligned contact (SAC) etch a bottom S/D recess through the ILD to expose the bottom S/D layer, the etch removing at least portion of the gate spacer and the high-k metal gate layer; and forming a bottom S/D contact spacer on sides of the bottom S/D recess.