Self-Aligned Source/Drain Junction for Vertical FET
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Solution Overview
Problem
Vertical FinFET devices face challenges in achieving uniform channel doping due to non-uniform dopant diffusion from heavily doped source/drain regions, leading to degraded electrical performance.
Innovation Solution
The method involves forming self-aligned dielectric layers, such as PSG or BSG, on the sides of fins or nanowires to facilitate dopant diffusion, resulting in uniform channel doping by reducing the distance and increasing the surface area for dopant distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dopant diffusion is performed from heavily doped source/drain regions in vertical FinFET devices, then doping is achieved, but uniform channel doping is difficult to achieve due to non-uniform dopant distribution
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the source/drain regions and the channel regions. This dielectric layer serves as a controlled dopant source that enables uniform dopant diffusion into the channel regions, resolving the non-uniform doping issue while maintaining electrical performance
Solution Approach 2:
The dielectric layer is formed and doped in advance before the final channel doping step. This preliminary doping of the dielectric layer allows for controlled and uniform dopant release into the channel regions during subsequent thermal processing, achieving uniform channel doping
2Ease of manufacture
If horizontal FinFET architecture is used, then fabrication is simpler, but contact gate pitch is limited between 30 nm and 50 nm due to scaling plateaus
Solution Approach 1:
The invention transitions from horizontal FinFET architecture to vertical FinFET architecture. This dimensional change allows the gate to extend vertically along the fin structure, decoupling the gate length from the contact gate pitch and enabling smaller pitch values while maintaining fabrication feasibility
3Length of moving object
If vertical FinFET architecture is adopted, then contact gate pitch is reduced and MOL resistance is lowered, but uniform channel doping becomes more challenging
Solution Approach 1:
The dielectric layer acts as a mediator that enables controlled dopant diffusion in the vertical architecture. By positioning the dielectric layer adjacent to the channel regions and pre-doping it, uniform dopant distribution is achieved despite the vertical geometry challenges
Solution Approach 2:
The dielectric layer is selectively positioned and doped in specific regions adjacent to the channel regions. This local doping approach ensures that dopant is released only where needed, achieving uniform channel doping in the vertical FinFET structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures more uniform dopant concentrations in the channel regions, enhancing the electrical uniformity and performance of vertical FETs by decoupling gate length from contact gate pitch and reducing middle-of-line resistance.
Implementation Method 1
doping comprises diffusing a dopant from the lower dielectric layer into the portions of the plurality of channel regions
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a bottom source/drain region on a substrate, forming a semiconductor layer on the bottom source/drain region, patterning the semiconductor layer into a plurality of channel regions extending vertically with respect to the substrate, conformally forming a lower dielectric layer on the patterned semiconductor layer, forming a lower spacer layer on a portion of the lower dielectric layer, removing an exposed portion of the lower dielectric layer, forming a gate structure around the plurality of channel regions and on the lower spacer layer, and doping portions of the plurality of channel regions corresponding to the lower spacer layer, wherein the doping comprises diffusing a dopant from the lower dielectric layer into the portions of the plurality of channel regions.