Vertical FET Channel Disabling for Sheet Depopulation Without Stress Loss
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Solution Overview
Problem
Conventional methods for sheet depopulation in semiconductor devices, such as field-effect transistors, face challenges in maintaining epitaxial stress for P-FET regions while reducing stress loss and avoiding dislocations in the upper epitaxial region, which affects performance.
Innovation Solution
A bottom dielectric is formed from the backside of the wafer for sheet depopulation, allowing for independent control of sheet numbers in both N-FET and P-FET regions without stress loss, using techniques like double-patterning or multi-patterning processes to pattern nanostructure devices like GAAFETs or NSFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional sheet depopulation methods are used, then the number of sheets is reduced, but epitaxial stress is lost and dislocations occur in the upper epitaxial region
Solution Approach 1:
The patent segments the channel sheets into enabled and disabled groups by forming dielectric structures between specific sheets. This allows selective depopulation of certain sheets while preserving others, maintaining epitaxial stress in the remaining enabled sheets while reducing the total number of active channels.
Solution Approach 2:
Dielectric structures are introduced as intermediary elements between channel sheets to disable specific sheets. These dielectric structures act as mediators that electrically isolate selected sheets from the source and drain regions, enabling sheet depopulation without affecting the structural integrity and stress state of the remaining sheets.
2Loss of energy
If sheet depopulation is performed to reduce stress loss, then performance is improved, but dislocations are formed in the upper epitaxial region
Solution Approach 1:
The patent performs preliminary actions by forming the dielectric structures and patterned doping regions before final device operation. The selective doping is performed in advance to create disabled sheets that will prevent dislocation formation during subsequent processing or operation, thereby preventing rather than correcting the harmful effect.
Solution Approach 2:
The patent converts the potential harm of sheet depopulation (which could cause dislocations) into a benefit by using the depopulation process to create a controlled structure where dielectric structures and patterned doping work together to prevent dislocations while still achieving stress loss reduction through selective sheet disabling.
3Adaptability or versatility
If independent control of sheet numbers in N-FET and P-FET regions is implemented, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by implementing different sheet configurations in different regions of the device. N-FET and P-FET regions can have different numbers of enabled or disabled sheets tailored to their specific performance requirements. The dielectric structures and doping patterns are locally customized for each region while using the same fundamental fabrication processes.
Data Source
AI summary
A device includes a vertical stack of semiconductor nanostructures, a gate structure, a first epitaxial region and a dielectric structure. The gate structure wraps around the semiconductor nanostructures. The first epitaxial region laterally abuts a first semiconductor nanostructure of the semiconductor nanostructures. The dielectric structure laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.