Vertical Transport FET on Silicon with Defined Junctions
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Solution Overview
Problem
The challenge in semiconductor technology is the limitation of conventional fabrication techniques in scaling down devices, particularly for vertical transport field-effect transistors (VTFETs), which face issues due to lattice mismatch and dislocation defects when combining semiconductor materials with different lattice constants, hindering the development of high-density and high-performance integrated circuits.
Innovation Solution
The use of aspect ratio trapping (ART) techniques to grow vertical non-silicon fins on a silicon substrate, forming VTFET structures with defined junctions by depositing multiple dielectric layers to determine the positions of source/drain, gate, and metal contacts, and employing epitaxial growth to minimize dislocation defects by forming high-aspect-ratio trenches that trap defects on the sidewalls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional fabrication techniques are used for scaling, then manufacturing simplicity is maintained, but device scaling and density are limited
Solution Approach 1:
The patent transitions from conventional planar FET structures to vertical FET structures by growing semiconductor fins vertically on silicon substrates. This dimensional change enables continued device scaling and density improvement while managing the complexities of fabricating heterostructure devices with defined junctions.
2Productivity
If vertical FET structures are implemented, then circuit density is improved, but layout-level challenges and fabrication complexity increase
Solution Approach 1:
The patent employs aspect ratio trapping by controlling the height-to-width ratio of vertical fins to trap dislocation defects. By changing the geometric parameters of the fin structure (high aspect ratio), the patent achieves defect-free semiconductor layers while maintaining the vertical structure's density benefits.
3Reliability
If heterostructure materials are combined, then device performance is improved, but lattice mismatch and dislocation defects occur
Solution Approach 1:
The patent converts the harmful effect of lattice mismatch and dislocation defects into a beneficial trapping mechanism. By designing vertical fins with specific aspect ratios, dislocation defects are trapped on the sidewalls of the fins rather than propagating through the device, thereby achieving defect-free active regions while maintaining heterostructure performance benefits.
Solution Approach 2:
The patent creates different structural qualities in different regions: the vertical fins have high aspect ratios to trap defects, while the regions between fins maintain the heterostructure composition for device performance. This local differentiation allows simultaneous achievement of defect mitigation and high performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of VTFET structures with reduced circuit footprint and improved density, overcoming lattice mismatch issues and achieving defect-free layers, thus enhancing the performance and reliability of semiconductor devices.
Implementation Method 1
A vertical fin structure is formed by epitaxially growing material within the trench on the top of the substrate
Implementation Method 2
the height and width dimensions of the trench are selected in accordance with an aspect ratio trapping process
Data Source
AI summary
A method for fabricating a semiconductor structure includes the following steps. A plurality of dielectric layers is formed on a substrate, wherein the material composition and layer positioning of each of the plurality of dielectric layers are selected to enable defined junctions for one or more features of the semiconductor structure. A trench is formed through each of the plurality of dielectric layers to the top of the substrate, wherein the height and width dimensions of the trench are selected in accordance with an aspect ratio trapping process. A vertical fin structure is formed by epitaxially growing material within the trench on the top of the substrate. In further steps, gate stack and source/drain regions are formed around the vertical fin structure in accordance with the positioning of the plurality of dielectric layers. The resulting semiconductor structure, in one or more examples, is a vertical transport field-effect transistor.