Vertical FET Shaped Spacer Parasitic Capacitance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Vertical field effect transistors (VFETs) face increased parasitic capacitance due to the direct overlapping of drain epitaxy with gate conductors, which affects device performance, especially at node sizes of 7 nm and beyond.
Innovation Solution
A shaped spacer is formed to cover the lower portion and sides of the second source/drain region, providing additional dielectric material between the gate conductor and the source/drain region to reduce parasitic capacitance, and the method involves forming a semiconductor fin, depositing a dielectric layer, etching to create contoured side walls, and recessing to expose the fin, followed by growing a source/drain region and forming a gate dielectric and conductor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If thin spacers and high-k gate dielectric are used to separate drain epitaxy with gate conductors, then device integration is achieved, but parasitic capacitance remains significant and affects device performance
Solution Approach 1:
The spacer is designed with non-uniform thickness, being thickest at the lower portion of the source/drain region and gradually thinning toward the upper portion. This local variation in spacer thickness provides enhanced dielectric separation where parasitic capacitance is most significant (at the lower portion near the gate conductor overlap) while maintaining acceptable device integration elsewhere
Solution Approach 2:
The invention transitions from a conventional planar or simple vertical spacer structure to a three-dimensional shaped spacer with contoured sides. The spacer extends laterally and vertically with optimized geometry, adding spatial dimensions to the separation between gate conductor and source/drain region, thereby reducing parasitic capacitance through increased dielectric material volume in critical areas
2Area of stationary object
If direct overlapping of drain epitaxy with gate conductors is used, then chip area is reduced, but parasitic capacitance increases significantly
Solution Approach 1:
The shaped spacer acts as an intermediary dielectric structure positioned between the gate conductor and the source/drain region. This intermediate element provides additional electrical separation and reduces direct capacitive coupling, allowing the device to maintain compact overlapping geometry while mitigating parasitic capacitance effects
Solution Approach 2:
The device structure combines multiple materials including the shaped spacer material (dielectric), high-k gate dielectric, and conductive materials in a composite architecture. The shaped spacer material is specifically selected and positioned to provide optimal dielectric properties for reducing parasitic capacitance while maintaining overall device functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The shaped spacer effectively reduces parasitic capacitance by providing adequate dielectric material, improving electrical isolation and handling of capacitance, resulting in enhanced device performance with a significant reduction in parasitic capacitance, as demonstrated by a 65% reduction in estimated parasitic capacitance compared to conventional structures.
Implementation Method 1
One issue with VFETs is increased parasitic capacitance due to direct overlapping of drain epitaxy with gate conductors
Implementation Method 2
A shaped spacer is configured to cover a lower portion and sides of the second source/drain region to reduce parasitic capacitance between the gate conductor and the second source/drain region
Data Source
AI summary
A vertical transistor includes a first source/drain region and a second source/drain region vertically disposed relative to the first source/drain region and coupled to the first source/drain region by a fin. A gate dielectric is formed on the fin, and a gate conductor is formed on the gate dielectric in a region of the fin. A shaped spacer is configured to cover a lower portion and sides of the second source/drain region to reduce parasitic capacitance between the gate conductor and the second source/drain region.