Uniform Vertical FET Spacer Formation via Selective Oxidation
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Solution Overview
Problem
The challenge in fabricating vertical field effect transistors (VFETs) lies in forming uniform spacers, as conventional sidewall spacer formation methods are not applicable due to the horizontal spacer arrangement in VFET structures, making it difficult to achieve consistent insulation between gate and source/drain regions.
Innovation Solution
The solution involves forming a film stack with SiGe layers on a substrate, patterning vertical structures, and using selective wet etching to create vertical fins, followed by simultaneous low-temperature oxidation to form spacers around both source and drain regions with uniform thickness, leveraging differing oxidation rates to minimize oxidation around the fins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional sidewall spacer formation methods are used, then the fabrication process is simple, but uniform spacer thickness cannot be achieved in VFET structures
Solution Approach 1:
The patent changes the chemical parameters of the oxidation process by using selective oxidation conditions that exploit the different oxidation rates between SiGe and silicon materials. This allows uniform spacer formation on SiGe source/drain regions while minimizing oxidation on silicon vertical fins, achieving precise spacer thickness control without complex multi-step processes
Solution Approach 2:
The patent replaces the mechanical/physical deposition-based spacer formation method with a chemical oxidation-based method. Instead of depositing spacer material and etching, the process uses controlled oxidation to grow spacers in situ, simplifying the fabrication steps while improving uniformity
2Reliability
If oxidation is performed to form spacers, then insulation between gate and source/drain is improved, but oxidation may also occur around vertical fins reducing precision
Solution Approach 1:
The patent applies local quality by creating different oxidation conditions for different regions of the structure. The SiGe source/drain regions are selectively oxidized to form spacers, while the silicon vertical fins are protected from oxidation through the selective nature of the oxidation process, ensuring spacers form only where needed with consistent thickness
Solution Approach 2:
The patent utilizes composite material properties by combining SiGe layers with silicon layers in a film stack structure. The different material compositions (SiGe vs. silicon) enable selective oxidation behavior, allowing spacers to form on SiGe regions while silicon regions remain unaffected, achieving both insulation and precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for improved insulation performance by ensuring uniform spacer thickness, enhancing device performance and simplifying the fabrication process by enabling simultaneous source and drain formation, and spacer formation around the vertical structure.
Implementation Method 1
performing a low temperature oxidation on the semiconductor structure to create spacers around the source and the drain
Implementation Method 2
selectively wet etching the silicon layer to form a plurality of vertical fins, the vertical fins having vertical sidewalls
Data Source
AI summary
Aspects of the disclosure include a semiconductor structure that includes a vertical fin structure having a top portion, a bottom portion, vertical side walls, a source area in contact with the vertical fin structure, a drain area in contact with the vertical fin structure, a plurality of spacers comprising a first oxide layer in contact with the source area, and a second oxide layer in contact with the drain area. The first oxide layer can have a thickness that is equal to a thickness of the second oxide layer.