Self-Aligned Vertical FET Spacerless Gate Fabrication
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Solution Overview
Problem
Conventional vertical FET manufacturing processes, particularly those using high-k dielectrics, face challenges with threshold voltage shifts due to high-temperature steps, affecting PMOS transistor performance, and lack compatibility with gate-last approaches.
Innovation Solution
A method of fabricating a vertical field effect transistor involving the formation of a semiconductor nanowire with epitaxial source and drain regions and a conformal dielectric gate stack, using sacrificial layers to create a dummy gate structure and minimize parasitic capacitance, while being compatible with a gate-last process flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k dielectric materials are used in vertical FET manufacturing, then device performance is improved, but threshold voltage shifts occur due to high-temperature processing steps
Solution Approach 1:
The patent applies preliminary action by forming the gate structure (either as a sacrificial dummy gate or as the final gate) before depositing the high-k dielectric material. This sequence allows the gate to be established prior to high-temperature processing, preventing threshold voltage shifts that would occur if the gate were formed after such processing. The gate-first approach enables the gate to serve as a reference structure during subsequent dielectric deposition and processing steps.
Solution Approach 2:
The patent inverts the conventional gate-last sequence by using a gate-first approach where the gate structure is formed before the high-k dielectric. This inversion resolves the threshold voltage shift problem by ensuring the gate is already in place and stable before exposure to high-temperature processing that follows dielectric deposition, thereby eliminating the adverse interaction between high-k materials and the gate that causes voltage shifts.
2Ease of manufacture
If conventional gate-last processes are used, then manufacturing flexibility is improved, but PMOS transistor performance deteriorates due to threshold voltage shifts
Solution Approach 1:
The patent applies preliminary action by establishing the gate structure before depositing high-k dielectrics in PMOS fabrication. This preliminary gate formation prevents the threshold voltage shifts that plague conventional gate-last PMOS processes, while still maintaining manufacturing flexibility through the use of sacrificial layers that can be selectively removed to form the final gate structure.
Solution Approach 2:
The patent uses sacrificial layers as intermediary structures that temporarily serve as dummy gates during high-k dielectric deposition. These sacrificial layers mediate between the need for gate-last processing flexibility and the need to prevent threshold voltage shifts, allowing the high-k material to be deposited conformally over a gate structure that is later replaced or modified to form the final gate.
3Ease of manufacture
If lithography is used to define channel length, then manufacturing simplicity is improved, but dimensional precision deteriorates
Solution Approach 1:
The patent replaces the lithographic mechanical patterning system with a self-aligned epitaxial growth system. Instead of using lithography to define channel length, the channel dimensions are determined by the precise thickness control of epitaxially grown semiconductor layers, which offer superior dimensional precision while simplifying the manufacturing process by eliminating alignment steps.
Solution Approach 2:
The patent changes the controlling parameter for channel length from lithographic pattern dimensions to epitaxial layer thickness. This parameter change enables precise dimensional control because epitaxial growth can control thickness at the nanometer and sub-nanometer scale, far exceeding the resolution limits of conventional lithography, while maintaining manufacturing simplicity through a self-aligned process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise dimensional control and improved PMOS performance by reducing parasitic capacitance and avoiding adverse threshold voltage shifts, ensuring compatibility with gate-last processes.
Implementation Method 1
source and drain regions are deposited via epitaxy directly over respective portions of the nanowire
Data Source
AI summary
A method of making a vertical field effect transistor includes forming a semiconductor nanowire that extends from a substrate surface. A first sacrificial layer is deposited over the substrate surface, and a second sacrificial layer is deposited over the first sacrificial layer such that each of the first and second sacrificial layers are formed peripheral to the nanowire. The second sacrificial layer is then patterned to form a dummy gate structure. Thereafter, the first sacrificial layer is removed and source and drain regions are deposited via epitaxy directly over respective portions of the nanowire.