Compact Model for Vertical FET Stacks with Shared Thermal Impedance
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Solution Overview
Problem
Conventional modeling techniques fail to accurately represent the shared gate resistance and heat dynamics of vertically stacked field-effect transistors (FETs), as the operation of one FET can significantly impact adjacent FETs due to shared gate networks and heat dissipation.
Innovation Solution
A method involving the generation of thermal and electrical equivalence circuit models for vertically stacked FETs, followed by the creation of a compact model that determines thermal and electrical impedances, including shared thermal impedance, to accurately model inter-FET dynamics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional modeling techniques are used for vertical stack FETs, then individual FET operation can be modeled, but shared gate resistance and heat dynamics between adjacent FETs cannot be accurately represented
Solution Approach 1:
The patent merges individual FET models with shared gate network models and shared thermal impedance models to create a unified compact model. This combining approach allows the model to represent both individual FET characteristics and the coupled behavior of shared gates and heat dissipation paths, resolving the contradiction between modeling accuracy and complexity.
Solution Approach 2:
The compact model is designed to serve multiple functions simultaneously: it models electrical characteristics of individual FETs, captures shared gate resistance effects, represents heat dissipation dynamics, and predicts thermal coupling between adjacent FETs. This multi-functionality achieves high modeling accuracy without requiring separate specialized models for each phenomenon.
2Area of stationary object
If vertical stack FET configuration is used, then space efficiency is improved, but heat dissipation from one FET impacts adjacent FETs
Solution Approach 1:
The patent introduces shared thermal impedance as an intermediary element in the thermal equivalence circuit model. This shared thermal impedance acts as a mediator that represents the heat transfer path between adjacent FETs through the shared gate network, allowing the harmful heat impact to be quantified and modeled accurately without changing the physical vertical stack configuration.
3Temperature
If lateral FET configuration is used, then heat dissipation is improved, but space utilization is reduced
Solution Approach 1:
The patent transitions from modeling lateral FET configurations (2D plane layout) to vertical stack FET configurations (3D stacked architecture). This dimensional change allows better space utilization by stacking FETs vertically, while the thermal equivalence circuit model with shared thermal impedance accounts for the heat dissipation characteristics of this vertical arrangement.
Data Source
AI summary
Techniques are provided for multi-FET vertical stack modeling. In one embodiment, the techniques involve generating a first thermal equivalence circuit model of a first transistor of a vertical stack configuration, wherein the first thermal equivalence circuit model includes a first thermal impedance, generating a second thermal equivalence circuit model of a second transistor of the vertical stack configuration, wherein the second thermal equivalence circuit model includes a second thermal impedance, generating a compact model based on the first thermal equivalence circuit model and the second thermal equivalence circuit model, determining, based on the compact model and transistor data, the first thermal impedance and the second thermal impedance, and determining, based on the compact model and the transistor data, a third thermal impedance, wherein the third thermal impedance represents a shared thermal impedance of the first thermal equivalence circuit model and the second thermal equivalence circuit model.