Vertical FET Stack Offset Contacts for IC Density
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Solution Overview
Problem
The increasing density of integrated circuits (ICs) leads to difficulties in design and fabrication due to the complexity of routing conductive traces and the need for precise alignment of source and drain contacts, which can result in manufacturing errors and reduced packing efficiency.
Innovation Solution
A vertical stack of field-effect transistors (FETs) with fully independent source and drain contacts and a common gate, where the source and drain contacts of upper FETs are offset along the gate direction from those of underlying FETs, allowing for increased access and flexibility in routing and enabling a more efficient packing of conductive traces in a single direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If increasing IC density is implemented, then speed and functionality are improved, but design and fabrication complexity increases
Solution Approach 1:
The patent transitions from planar 2D routing to 3D vertical stacking, allowing conductive traces to be routed in multiple layers and directions. This dimensional change enables higher IC density without proportionally increasing routing complexity, as traces can be stacked vertically rather than competing for lateral space.
Solution Approach 2:
The patent segments the routing path into multiple discrete conductive trace layers stacked vertically. Each layer can be independently routed and connected via vias, allowing complex connections to be broken down into simpler segmentable paths that reduce overall routing difficulty.
2Productivity
If increasing IC density is implemented, then functionality is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements nested conductive trace structures where multiple trace layers are stacked vertically with overlapping footprints. This nesting allows traces to share common alignment references and reduces the cumulative alignment error that would accumulate in purely lateral routing paths.
Solution Approach 2:
The patent merges multiple routing functions into shared vertical trace structures. By combining lateral and vertical routing segments into integrated 3D paths, the number of separate alignment operations is reduced, thereby lowering cumulative precision requirements.
3Ease of manufacture
If conventional planar routing is used, then fabrication is simpler, but packing efficiency decreases
Solution Approach 1:
The patent adds the vertical dimension to conventional planar routing, creating 3D stacked conductive trace structures. This allows multiple routing paths to occupy the same lateral footprint by stacking them vertically, dramatically improving packing efficiency while maintaining fabrication compatibility through standard layer-by-layer processing.
Solution Approach 2:
The patent uses thin film conductive traces deposited in multiple layers to create flexible 3D routing paths. These thin film structures can be precisely controlled during deposition and allow complex 3D geometries to be fabricated using standard thin film processing techniques.
Data Source
AI summary
A structure includes a first transistor of a first type, the first transistor including a first channel, a first conductive segment, and a second conductive segment, a second transistor of a second type, the second transistor including a second channel, a third conductive segment, and a fourth conductive segment, and a gate. The first channel extends through the gate between the first and second conductive segments, the second channel extends through the gate between the third and fourth conductive segments and is aligned with the first channel at a center of the first transistor, the first and third conductive segments extend away from the center of the first transistor in opposite directions, and the second and fourth conductive segments extend away from the center of the first transistor in opposite directions.