Vertical FET Stack Layout for Lower Stray Capacitance
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Solution Overview
Problem
The complexity of manufacturing semiconductor devices at a miniaturized scale leads to increased yield loss, reduced reliability of electrical interconnections, and low testing coverage, necessitating improvements in device structure and manufacturing methods to enhance robustness, reduce costs, and shorten processing time.
Innovation Solution
A semiconductor device design featuring a vertical stack of upper and lower FETs with a common gate and independently controlled source/drain regions, utilizing separate metal power rails and a shortened gate to reduce resistance, power consumption, and stray capacitance, while improving electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor device structures are used at miniaturized scale, then manufacturing complexity increases, but device performance and reliability deteriorate
Solution Approach 1:
The patent transitions from planar 2D device layout to vertical 3D stacking architecture. Multiple FETs are stacked vertically with shared gates, enabling higher functional density while reducing the horizontal footprint. This dimensional change allows complex functionality to be achieved through vertical integration rather than horizontal expansion, thereby improving reliability without proportionally increasing manufacturing complexity.
Solution Approach 2:
The patent merges multiple FET structures into a vertical stack with common gates. The first and second FETs share gate structures and control mechanisms, reducing the total number of independent components. This merging approach simplifies the control architecture and reduces the number of interconnections required, thereby improving reliability while managing manufacturing complexity.
2Loss of energy
If gate length is shortened to reduce stray capacitance, then power consumption decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent reduces stray capacitance by minimizing the horizontal overlap area between gates and source/drain regions through vertical stacking. The gate length is optimized to be substantially equal to the active region length, reducing parasitic capacitance without requiring extremely short gate lengths that would demand excessive manufacturing precision. The vertical architecture achieves capacitance reduction through spatial arrangement rather than extreme dimensional scaling.
3Productivity
If functional density is increased to improve device capability, then circuit complexity increases, but testing coverage and yield decrease
Solution Approach 1:
The patent segments the semiconductor device into distinct vertical layers: first FET, second FET, isolation regions, and conductive interconnections. Each FET is independently structured with defined source, drain, and gate regions. This segmentation allows each component to be manufactured and characterized separately, simplifying testing and quality control while achieving high functional density through vertical integration.
Solution Approach 2:
The patent achieves high functional density by stacking FETs vertically rather than placing them horizontally in complex planar circuits. This vertical arrangement reduces the number of interconnections and routing layers required, simplifying the overall circuit complexity while maintaining high device capability. The vertical stack enables dense integration with fewer inter-layer vias and simpler signal routing compared to equivalent planar designs.
Data Source
AI summary
A semiconductor structure includes: a first transistor and a second transistor. The first transistor includes: a first gate; a first and a second source/drain regions; and a first conductive line and a second conductive line arranged in the first layer. The second transistor is arranged vertically overlapping the first transistor and includes: a second gate; a third and a fourth source/drain regions; and a third conductive line and a fourth conductive line arranged in the second layer and electrically coupled to the third source/drain region and the fourth source/drain region, respectively. The semiconductor structure further includes a first conductive via arranged between the first layer and the second layer and electrically connecting the first source/drain region to the third source/drain region.