Vertical FET Strained Channel via Lattice Mismatch Stressors
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Solution Overview
Problem
The vertical orientation of field effect transistors (FETs) poses challenges in controlling gate length, spacer thickness, and extension doping profile, making it difficult to introduce strain effectively due to the relaxed channel material geometry, which affects mobility and device performance.
Innovation Solution
A sigma-etched channel region is formed near the bottom terminal of the vertical FET, and an epitaxially grown stressor region with a different lattice constant is embedded between the channel and heavily doped source/drain regions to induce strain, improving hole or electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a vertical FET structure is used to reduce device footprint, then the device area is reduced, but it becomes difficult to introduce strain effectively due to relaxed channel material geometry
Solution Approach 1:
The patent applies local quality by introducing stressor regions with different lattice constants at specific locations within the vertical FET structure. Instead of attempting to strain the entire channel uniformly, stressors are placed locally at the source/drain regions to induce strain in the channel material through lattice mismatch, thereby overcoming the geometric constraints of the vertical configuration.
Solution Approach 2:
The patent employs composite materials by combining the channel material with stressor regions made of different semiconductor materials having distinct lattice constants. This composite structure allows the channel to maintain its vertical geometry while the integrated stressors provide the necessary strain through material property differences rather than geometric constraints.
2Ease of manufacture
If the channel material geometry is relaxed to accommodate vertical orientation, then device integration is simplified, but mobility control is adversely affected
Solution Approach 1:
The patent utilizes parameter changes by varying the lattice constant parameter of the channel material through integration with stressor regions. By selecting stressor materials with specific lattice constants that differ from the channel material, the patent induces tensile or compressive strain to modify carrier mobility, thereby maintaining mobility control despite the relaxed vertical geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces variations in FET fabrication and enhances mobility by applying compressive or tensile strain to the channel region, leading to improved device performance in vertical FETs.
Implementation Method 1
The stressor region has a different lattice constant compared to the channel region material so as to induce a strain upon the channel region
Data Source
AI summary
A vertical field effect transistor (FET) includes a first source/drain region formed on an upper surface of a semiconductor substrate, and a semiconductor channel material that extends vertically from the first source/drain region to a second source/drain region. A metal gate structure encapsulating the semiconductor channel material. The vertical FET further includes a stressor region that contacts the semiconductor channel material and the first source/drain region. The combination of the semiconductor channel material and the stressor region defines a total length of a strained channel region of the vertical field effect transistor.